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FM27C512N55L PDF预览

FM27C512N55L

更新时间: 2024-10-02 19:32:27
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD OTP只读存储器输入元件光电二极管输出元件内存集成电路
页数 文件大小 规格书
10页 98K
描述
OTP ROM, 64KX8, 55ns, CMOS, PDIP28, PLASTIC, DIP-28

FM27C512N55L 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.46
最长访问时间:55 ns其他特性:TTL/CMOS COMPATIBLE INPUTS/OUTPUTS
JESD-30 代码:R-PDIP-T28长度:35.942 mm
内存密度:524288 bit内存集成电路类型:OTP ROM
内存宽度:8功能数量:1
端子数量:28字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:5.334 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:15.24 mmBase Number Matches:1

FM27C512N55L 数据手册

 浏览型号FM27C512N55L的Datasheet PDF文件第2页浏览型号FM27C512N55L的Datasheet PDF文件第3页浏览型号FM27C512N55L的Datasheet PDF文件第4页浏览型号FM27C512N55L的Datasheet PDF文件第5页浏览型号FM27C512N55L的Datasheet PDF文件第6页浏览型号FM27C512N55L的Datasheet PDF文件第7页 
January 2000  
FM27C512  
524,288-Bit (64K x 8) High Performance CMOS EPROM  
The FM27C512 is one member of a high density EPROM Family  
which range in densities up to 4 Megabit.  
General Description  
The FM27C512 is a high performance 512K UV Erasable Electri-  
cally Programmable Read Only Memory (EPROM). It is manufac-  
tured using Fairchild’s proprietary CMOS AMG™ EPROM tech-  
nology for an excellent combination of speed and economy while  
providing excellent reliability.  
Features  
I High performance CMOS  
— 90 ns access time  
I Fast turn-off for microprocessor compatibility  
TheFM27C512providesmicroprocessor-basedsystemsstorage  
capacity for portions of operating system and application soft-  
I Manufacturers identification code  
ware. Its 90 ns access time provides no wait-state operation with  
high-performance CPUs. The FM27C512 offers a single chip  
solution for the code storage requirements of 100% firmware-  
based equipment. Frequently-used software routines are quickly  
executed from EPROM storage, greatly enhancing system utility.  
I JEDEC standard pin configuration  
— 28-pin PDIP package  
— 32-pin chip carrier  
— 28-pin CERDIP package  
The FM27C512 is configured in the standard JEDEC EPROM  
pinoutwhichprovidesaneasyupgradepathforsystemswhichare  
currently using standard EPROMs.  
Block Diagram  
Data Outputs O - O  
0
7
V
CC  
GND  
V
PP  
OE  
Output Enable and  
Chip Enable Logic  
CE/PGM  
Output  
Buffers  
Y Decoder  
524,288-Bit  
Cell Matrix  
A
- A  
15  
0
Address  
Inputs  
X Decoder  
DS800035-1  
AMG is a trademark of WSI, Inc.  
1
© 1998 Fairchild Semiconductor Corporation  
FM27C512  
www.fairchildsemi.com  

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