Datasheet > FM25P16-G

FM25P16-G

更新时间： 2024-01-14 17:50:59

品牌	Logo	应用领域
铁电 - RAMTRON		内存集成电路
页数	文件大小	规格书
14页	205K
描述
Memory Circuit

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技术参数
数据手册

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FM25P16-G 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.32.00.71
风险等级：	5.84	内存集成电路类型：	MEMORY CIRCUIT
Base Number Matches：	1

FM25P16-G 数据手册

FM25P16 - 16Kb Ultra Low Power FRAM

WREN - Set Write Enable Latch

Data Transfer

All data transfers to and from the FM25P16 occur in

8-bit groups. They are synchronized to the clock

signal (SCK), and they transfer most significant bit

(MSB) first. Serial inputs are registered on the rising

edge of SCK. Outputs are driven from the falling

edge of SCK.

The FM25P16 will power up with writes disabled.

The WREN command must be issued prior to any

write operation. Sending the WREN op-code will

allow the user to issue subsequent op-codes for

write operations. These include writing the status

Command Structure

Sending the WREN op-code causes the internal

Write Enable Latch to be set. A flag bit in the status

WEL=1 indicates that writes are permitted.

Attempting to write the WEL bit in the status

operation will automatically clear the write-enable

latch and prevent further writes without another

WREN command. Figure 5 below illustrates the

WREN command bus configuration.

There are six commands called op-codes that can be

issued by the bus master to the FM25P16. They are

listed in the table below. These op-codes control the

functions performed by the memory. They can be

divided into three categories. First, there are

commands that have no subsequent operations. They

perform a single function such as to enable a write

operation. Second are commands followed by one

byte, either in or out. They operate on the status

memory transactions followed by an address and one

or more bytes of data.

WRDI - Write Disable

The WRDI command disables all write activity by

clearing the Write Enable Latch. The user can verify

that writes are disabled by reading the WEL bit in

the status register and verifying that WEL=0. Figure

6 illustrates the WRDI command bus configuration.

Table 1. Op-code Commands

Name

WREN

WRDI

RDSR

WRSR

READ

WRITE

RDID

Description

Set Write Enable Latch

Write Disable

Read Status Register

Write Status Register

Read Memory Data

Write Memory Data

Read Device ID

Op-code

00000110b

00000100b

00000101b

00000001b

00000011b

00000010b

10011111b

Figure 5. WREN Bus Configuration

Figure 6. WRDI Bus Configuration

Rev. 1.0

Dec. 2011

Page 5 of 14

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