Datasheet > FM25P16-G

FM25P16-G

更新时间： 2024-02-06 03:59:26

品牌	Logo	应用领域
铁电 - RAMTRON		内存集成电路
页数	文件大小	规格书
14页	205K
描述
Memory Circuit

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技术参数
数据手册

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FM25P16-G 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.32.00.71
风险等级：	5.84	内存集成电路类型：	MEMORY CIRCUIT
Base Number Matches：	1

FM25P16-G 数据手册

FM25P16 - 16Kb Ultra Low Power FRAM

Instruction Decode

Clock Generator

Control Logic

HOLD

SCK

Write Protect

511 x 32

FRAM Array

Instruction Register

Address Register

Counter

Data I/O Register

Nonvolatile Status

Figure 1. Block Diagram

PIN DESCRIPTION

Pin Name

I/O

Description

/CS

Input

Chip Select: This active low input activates the device. When high, the device enters

low-power standby mode, ignores other inputs, and all outputs are tri-stated. When

low, the device internally activates the SCK signal. A falling edge on /CS must occur

prior to every op-code.

SCK

Input

Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on

the rising edge and outputs occur on the falling edge. Since the device is static, the

clock frequency may be any value between 0 and 1 MHz and may be interrupted at

any time.

Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation

for another task. When /HOLD is low, the current operation is suspended. The device

ignores any transition on SCK or /CS. All transitions on /HOLD must occur while

/HOLD

SCK is low. If it is not used, the /HOLD pin should be tied to V_DD

/WP

Input

Write Protect: This active-low pin prevents write operations to the Status Register

only. A complete explanation of write protection is provided on pages 6 and 7. If it is

not used, the /WP pin should be tied to V_DD

Serial Input: All data is input to the device on this pin. The pin is sampled on the

rising edge of SCK and is ignored at other times. It should always be driven to a valid

logic level to meet I_DDspecifications.

* SI may be connected to SO for a single pin data interface.

Serial Output: This is the data output pin. It is driven during a read and remains tri-

stated at all other times including when /HOLD is low. Data transitions are driven on

the falling edge of the serial clock.

Output

* SO may be connected to SI for a single pin data interface.

VDD

VSS

Supply

Power Supply (1.8V to 3.6V)

Ground

Rev. 1.0

Dec. 2011

Page 2 of 14

123 4 5 6 7...14

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