November 2001
FM24C256 – 256K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
General Description
Features
FM24C256 is a 256Kbit CMOS non-volatile serial EEPROM
organized as 32K x 8 bit memory. This device confirms to
ExtendedIIC2-wireprotocolthatallowsaccessingofmemoryin
excessof16KbitonanIICbus.Thisserialcommunicationprotocol
usesaClocksignal(SCL)andaDatasignal(SDA)tosynchro-
nouslyclockdatabetweenamaster(e.g.amicrocontroller)anda
slave(EEPROM).FM24C256isdesignedtominimizepincount
andsimplifyPCboardlayoutrequirements.
I Extendedoperatingvoltage:2.7Vto5.5V
I Upto400KHzclockfrequencyat2.7Vto5.5V
I Lowpowerconsumption
—0.5mAactivecurrenttypical
—10µAstandbycurrenttypical
—1µAstandbycurrenttypical(Lversion)
—0.1µAstandbycurrenttypical(LZversion)
I Schmitttriggerinputs
FM24C256offershardwarewriteprotectionwherebytheentire
memoryarraycanbewriteprotectedbyconnectingWPpintoV
I 64bytepagewritemode
.
CC
I Selftimedwritecycle(6msmax)
I HardwareWriteProtectionfortheentirearray
I Endurance:upto100Kdatachanges
I DataRetention:Greaterthan40years
I Packages:8-PinDIPand8-PinSO
TheentirememorythenbecomesunalterableuntiltheWPpinis
switchedtoV
.
SS
“LZ”and“L”versionsofFM24C256offerverylowstandbycurrent
makingthemsuitableforlowpowerapplications.Thisdeviceis
offeredinSOandDIPpackages.
Fairchild EEPROMs are designed and tested for applications
requiringhighendurance,highreliabilityandlowpowerconsump-
tion.
I Temperaturerange
—Commercial:0 °Cto+70°C
—Industrial(E):-40 °Cto+85°C
—Automotive(V):-40 °Cto+125°C
Block Diagram
V
SS
WRITE
LOCKOUT
V
CC
H.V. GENERATION
TIMING &CONTROL
WP
START
STOP
SDA
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
2
E
PROM
ARRAY
XDEC
SCL
A2
A1
A0
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
D
OUT
DATA REGISTER
D
IN
1
©2001FairchildSemiconductorCorporation
FM24C256 Rev. D.1
www.fairchildsemi.com