Datasheet > FAN3228T

FAN3228T

更新时间： 2024-02-28 03:34:33

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		驱动器栅极栅极驱动
页数	文件大小	规格书
12页	459K
描述
Application Review and Comparative Evaluation of Low-Side Gate Drivers

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FAN3228T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	GREEN, SOIC-8	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	5.81
内置保护：	TRANSIENT	接口集成电路类型：	FULL BRIDGE BASED PERIPHERAL DRIVER
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	8
最高工作温度：	125 °C	最低工作温度：	-40 °C
输出电流流向：	SOURCE AND SINK	标称输出峰值电流：	3 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	12 V	认证状态：	Not Qualified
座面最大高度：	1.75 mm	子类别：	MOSFET Drivers
最大供电电压：	18 V	最小供电电压：	4.5 V
标称供电电压：	12 V	表面贴装：	YES
温度等级：	AUTOMOTIVE	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
断开时间：	0.022 µs	接通时间：	0.017 µs
宽度：	4 mm

FAN3228T 数据手册

AN-6069

APPLICATION NOTE

For a practical example, the gate-source voltage versus total

gate charge is reproduced from the Fairchild FCP20N60

power MOSFET datasheet in Figure 4. The curve was

produced using a test circuit that drives the gate of the

Device Under Test (DUT) with a small current source of

3mA. In this example, the gate charge needed to reach the

threshold voltage of 3V is approximately 7nC. The charge

required during interval t2, Q_GS2, is found to be 14nC – 7nC

V_DD

V_GS

V_PL

V_TH

= 7nC. In interval t3, the value of Q_GDis found to be Q_GD

46nC – 14nC = 32nC. In this typical case, the effect of Q_GD

on the switching loss is more significant than the

I_L

contribution resulting from Q_GS2

I_DS

FCP20N60

V_o

V_DS

-I_PL

-I_PK

time

I_G

t7 t8

t1 t2

Figure 5. MOSFET Turn Off with Inductive Load

Figure 4. V_GSvs. Q_gfor FCP20N60

In the t5 interval, I_Grises to discharge V_GSfrom V_DDto the

plateau level defined by (2). In the t6 interval, V_GSremains

at the plateau voltage while V_DSrises to the off state voltage.

The t6 interval lasts for a time approximated by:

With V_GSat final drive level, the value for Q_G,totalis known.

To find the average current required from the bias supply:

I_DD= Q_G⋅ f_SW

(6)

Q_GD

where f_swis the switching frequency of the power stage.

With the average current requirement known, the input

power drawn from the V_DDbias supply can be found as:

t6 = t_VDS,rise

(8)

I_G

In interval t7, the drain current I_DSfalls from the value of I_L

to 0 while V_GSfalls from V_PLto V_TH. This time interval is

given by:

P_dr= V_DD⋅I_DD= V_DD⋅Q_G⋅ f_SW

(7)

The circuit waveforms and current paths during inductive

load turn off are similar to those for turn on, but taken in a

reverse order. For brevity, the circuit waveforms are

indicated in Figure 5, but the current paths are not shown.

Q_GS,2

t7 = t_IDS,fall

(9)

I_G

In the t8 interval, V_GSis discharged from the threshold

voltage to zero.

An equation relating I_Gto the switching loss during the turn

off interval is given as:

⎛

⎜

⎝

⎞

⎟

⎠

× I_LOAD

Q _GD

I_G,t6

Q _{GS 2}

⎛

⎜

⎞

⎟

P_{SW .OFF}

⋅

(

f_SW

)

⋅

(10)

I_G,t7

⎝

⎠

Rev. 1.0.3 • 1/6/10

www.fairchildsemi.com

1 234 5 6 7...12

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