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FAN3225 PDF预览

FAN3225

更新时间: 2024-02-21 11:37:31
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器栅极栅极驱动
页数 文件大小 规格书
24页 1355K
描述
Dual 4A High-Speed, Low-Side Gate Drivers

FAN3225 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:HVSON, SOLCC8,.12,25Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:1.96Is Samacsys:N
内置保护:UNDER VOLTAGE接口集成电路类型:FULL BRIDGE BASED PERIPHERAL DRIVER
JESD-30 代码:S-XDSO-N8JESD-609代码:e4
长度:3 mm湿度敏感等级:1
功能数量:2端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
输出电流流向:SOURCE AND SINK封装主体材料:UNSPECIFIED
封装代码:HVSON封装等效代码:SOLCC8,.12,25
封装形状:SQUARE封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:12 V
认证状态:Not Qualified座面最大高度:0.8 mm
子类别:MOSFET Drivers最大供电电压:18 V
最小供电电压:4.5 V标称供电电压:12 V
表面贴装:YES温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)端子形式:NO LEAD
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

FAN3225 数据手册

 浏览型号FAN3225的Datasheet PDF文件第1页浏览型号FAN3225的Datasheet PDF文件第2页浏览型号FAN3225的Datasheet PDF文件第4页浏览型号FAN3225的Datasheet PDF文件第5页浏览型号FAN3225的Datasheet PDF文件第6页浏览型号FAN3225的Datasheet PDF文件第7页 
FAN3223  
FAN3224  
FAN3225  
Figure 4. Pin Assignments (Repeated)  
Pin Definitions  
Name  
Pin Description  
Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and  
CMOS INx threshold.  
ENA  
Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and  
CMOS INx threshold.  
ENB  
GND  
INA  
Ground. Common ground reference for input and output circuits.  
Input to Channel A.  
INA+ Non-Inverting Input to Channel A. Connect to VDD to enable output.  
INA-  
INB  
Inverting Input to Channel A. Connect to GND to enable output.  
Input to Channel B.  
INB+ Non-Inverting Input to Channel B. Connect to VDD to enable output.  
INB-  
Inverting Input to Channel B. Connect to GND to enable output.  
OUTA Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold.  
OUTB Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above UVLO threshold.  
Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is  
OUTA  
above UVLO threshold.  
Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is  
above UVLO threshold.  
OUTB  
Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected  
to GND; NOT suitable for carrying current.  
P1  
VDD  
Supply Voltage. Provides power to the IC.  
Output Logic  
FAN3223 (x=A or B)  
FAN3224 (x=A or B)  
FAN3225 (x=A or B)  
ENx  
INx  
ENx  
INx  
OUTx  
INx+  
INx  
OUTx  
OUTx  
0
0
1(7)  
0
0
1
0
0
0(7)  
0
0
0
1
0(7)  
0(7)  
1
0
1(7)  
0
0
1
0
0
0
1
1(7)  
1(7)  
0
1(7)  
1(7)  
1(7)  
0(7)  
1
0
1(7)  
1
Note:  
7. Default input signal if no external connection is made.  
© 2007 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5  
3

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