FAN3223 /FAN3224 /FAN3225
Dual 4-A High-Speed, Low-SideGate Drivers
Features
Description
The FA N3223-25 family of dual 4 A gate drivers is
designed to drive N-channel enhancement-mode
MOSFETs in low -side sw itching applications by
providing high peak current pulses during the short
sw itching intervals. The driver is available w ith either
TTL or CMOS input thresholds. Internal circuitry
provides an under-voltage lockout function by holding
the output LOW until the supply voltage is w ithin the
operating range. In addition, the drivers feature matched
internal propagation delays betw een A and B channels
for applications requiring dual gate drives w ith critical
timing, such as synchronous rectifiers. This also
enables connecting tw o drivers in parallel to effectively
double the current capability driving a single MOSFET.
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Industry-Standard Pinouts
4.5-V to 18-V Operating Range
5-A Peak Sink/Source at VDD =12 V
4.3-A Sink / 2.8-A Source at VOUT =6 V
Choice of TTL or CMOS Input Thresholds
Three Versions of Dual Independent Drivers:
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-
-
Dual Inverting + Enable (FAN3223)
Dual Non-Inverting + Enable (FAN3224)
Dual-Inputs (FAN3225)
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Internal Resistors Turn Driver Off If No Inputs
MillerDrive™ Technology
The FAN322X drivers incorporate MillerDrive™
architecture for the final output stage. This bipolar-
MOSFET combination provides high current during the
Miller plateau stage of the MOSFET turn-on / turn-off
process to minimize sw itching loss, w hile providing rail-
to-rail voltage sw ing and reverse current capability.
12-ns / 9-ns Typical Rise/Fall Times (2.2-nF Load)
Under 20-ns Typical Propagation Delay Matched
w ithin 1 ns to the Other Channel
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Double Current Capability by Paralleling Channels
8-Lead 3x3 mm MLP or 8-Lead SOIC Package
Rated from –40°C to +125°C Ambient
The FAN3223 offers two inverting drivers and the
FAN3224 offers tw o non-inverting drivers. Each device
has dual independent enable pins that default to ON if
not connected. In the FAN3225, each channel has dual
inputs of opposite polarity, w hich allow s configuration as
non-inverting or inverting w ith an optional enable
function using the second input. If one or both inputs are
left unconnected, internal resistors bias the inputs such
that the output is pulled LOW to hold the pow er
MOSFET OFF.
Automotive Qualified to AEC-Q100 (F085 Version)
Applications
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Sw itch-Mode Pow er Supplies
High-Efficiency MOSFET Sw itching
Synchronous Rectifier Circuits
DC-to-DC Converters
Motor Control
Automotive-Qualified Systems (F085 version)
ENA
1
8
ENA
1
8
1
8
ENB
ENB
INA+
INA-
+
-
INA
GND
INB
2
3
4
7
6
5
OUTA
VDD
INA
GND
INB
2
3
4
7
6
5
OUTA
VDD
INB+
GND
2
3
4
7
6
5
OUTA
VDD
A
B
A
B
A
B
+
-
OUTB
OUTB
OUTB
INB-
FAN3223
FAN3224
FAN3225
Figure 1.
Pin Configurations
© 2016 Semiconductor Components Industries, LLC
December-2017, Rev. 2
Publication Order Number
FAN3224/D
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