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FAN3225CMPX PDF预览

FAN3225CMPX

更新时间: 2024-11-26 02:57:23
品牌 Logo 应用领域
安森美 - ONSEMI PC驱动接口集成电路
页数 文件大小 规格书
29页 1974K
描述
Dual 4-A High-Speed, Low-Side Gate Drivers

FAN3225CMPX 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:HVSON, SOLCC8,.12,25Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:1.36Samacsys Confidence:3
Samacsys Status:ReleasedSamacsys PartID:166881
Samacsys Pin Count:9Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Small Outline No-leadSamacsys Footprint Name:MLP 3x3 8L (Power33)
Samacsys Released Date:2015-04-13 16:42:39Is Samacsys:N
内置保护:UNDER VOLTAGE接口集成电路类型:FULL BRIDGE BASED PERIPHERAL DRIVER
JESD-30 代码:S-XDSO-N8JESD-609代码:e4
长度:3 mm湿度敏感等级:1
功能数量:2端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
输出电流流向:SOURCE AND SINK封装主体材料:UNSPECIFIED
封装代码:HVSON封装等效代码:SOLCC8,.12,25
封装形状:SQUARE封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:12 V
认证状态:Not Qualified座面最大高度:0.8 mm
子类别:MOSFET Drivers最大供电电压:18 V
最小供电电压:4.5 V标称供电电压:12 V
表面贴装:YES温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)端子形式:NO LEAD
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

FAN3225CMPX 数据手册

 浏览型号FAN3225CMPX的Datasheet PDF文件第2页浏览型号FAN3225CMPX的Datasheet PDF文件第3页浏览型号FAN3225CMPX的Datasheet PDF文件第4页浏览型号FAN3225CMPX的Datasheet PDF文件第5页浏览型号FAN3225CMPX的Datasheet PDF文件第6页浏览型号FAN3225CMPX的Datasheet PDF文件第7页 
FAN3223 /FAN3224 /FAN3225  
Dual 4-A High-Speed, Low-SideGate Drivers  
Features  
Description  
The FA N3223-25 family of dual 4 A gate drivers is  
designed to drive N-channel enhancement-mode  
MOSFETs in low -side sw itching applications by  
providing high peak current pulses during the short  
sw itching intervals. The driver is available w ith either  
TTL or CMOS input thresholds. Internal circuitry  
provides an under-voltage lockout function by holding  
the output LOW until the supply voltage is w ithin the  
operating range. In addition, the drivers feature matched  
internal propagation delays betw een A and B channels  
for applications requiring dual gate drives w ith critical  
timing, such as synchronous rectifiers. This also  
enables connecting tw o drivers in parallel to effectively  
double the current capability driving a single MOSFET.  
.
.
.
.
.
.
Industry-Standard Pinouts  
4.5-V to 18-V Operating Range  
5-A Peak Sink/Source at VDD =12 V  
4.3-A Sink / 2.8-A Source at VOUT =6 V  
Choice of TTL or CMOS Input Thresholds  
Three Versions of Dual Independent Drivers:  
-
-
-
Dual Inverting + Enable (FAN3223)  
Dual Non-Inverting + Enable (FAN3224)  
Dual-Inputs (FAN3225)  
.
.
.
.
Internal Resistors Turn Driver Off If No Inputs  
MillerDrive™ Technology  
The FAN322X drivers incorporate MillerDrive™  
architecture for the final output stage. This bipolar-  
MOSFET combination provides high current during the  
Miller plateau stage of the MOSFET turn-on / turn-off  
process to minimize sw itching loss, w hile providing rail-  
to-rail voltage sw ing and reverse current capability.  
12-ns / 9-ns Typical Rise/Fall Times (2.2-nF Load)  
Under 20-ns Typical Propagation Delay Matched  
w ithin 1 ns to the Other Channel  
.
.
.
.
Double Current Capability by Paralleling Channels  
8-Lead 3x3 mm MLP or 8-Lead SOIC Package  
Rated from –40°C to +125°C Ambient  
The FAN3223 offers two inverting drivers and the  
FAN3224 offers tw o non-inverting drivers. Each device  
has dual independent enable pins that default to ON if  
not connected. In the FAN3225, each channel has dual  
inputs of opposite polarity, w hich allow s configuration as  
non-inverting or inverting w ith an optional enable  
function using the second input. If one or both inputs are  
left unconnected, internal resistors bias the inputs such  
that the output is pulled LOW to hold the pow er  
MOSFET OFF.  
Automotive Qualified to AEC-Q100 (F085 Version)  
Applications  
.
.
.
.
.
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Sw itch-Mode Pow er Supplies  
High-Efficiency MOSFET Sw itching  
Synchronous Rectifier Circuits  
DC-to-DC Converters  
Motor Control  
Automotive-Qualified Systems (F085 version)  
ENA  
1
8
ENA  
1
8
1
8
ENB  
ENB  
INA+  
INA-  
+
-
INA  
GND  
INB  
2
3
4
7
6
5
OUTA  
VDD  
INA  
GND  
INB  
2
3
4
7
6
5
OUTA  
VDD  
INB+  
GND  
2
3
4
7
6
5
OUTA  
VDD  
A
B
A
B
A
B
+
-
OUTB  
OUTB  
OUTB  
INB-  
FAN3223  
FAN3224  
FAN3225  
Figure 1.  
Pin Configurations  
© 2016 Semiconductor Components Industries, LLC  
December-2017, Rev. 2  
Publication Order Number  
FAN3224/D  

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