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FAN3224C PDF预览

FAN3224C

更新时间: 2024-01-26 14:44:32
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器栅极栅极驱动
页数 文件大小 规格书
12页 459K
描述
Application Review and Comparative Evaluation of Low-Side Gate Drivers

FAN3224C 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:SOIC-8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:4 weeks风险等级:1.35
内置保护:UNDER VOLTAGE高边驱动器:NO
接口集成电路类型:FULL BRIDGE BASED PERIPHERAL DRIVERJESD-30 代码:R-PDSO-G8
JESD-609代码:e4长度:4.9 mm
湿度敏感等级:1功能数量:2
端子数量:8最高工作温度:125 °C
最低工作温度:-40 °C输出电流流向:SOURCE AND SINK
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:12 V
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:MOSFET Drivers最大压摆率:0.95 mA
最大供电电压:18 V最小供电电压:4.5 V
标称供电电压:12 V表面贴装:YES
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

FAN3224C 数据手册

 浏览型号FAN3224C的Datasheet PDF文件第2页浏览型号FAN3224C的Datasheet PDF文件第3页浏览型号FAN3224C的Datasheet PDF文件第4页浏览型号FAN3224C的Datasheet PDF文件第6页浏览型号FAN3224C的Datasheet PDF文件第7页浏览型号FAN3224C的Datasheet PDF文件第8页 
AN-6069  
APPLICATION NOTE  
with magnetizing inductance LMAG. In both cases, the DC  
blocking capacitor CC is large enough so that its voltage is  
approximately constant.  
applied directly to the primary winding of T1, the  
transformer would saturate and not be able to transmit useful  
information. To prevent this, coupling capacitor CC is  
inserted in series with the primary winding to block the DC  
voltage while passing the AC portion of the VOUT signal.  
Transformers designed for pulse and gate drive applications  
usually specify a voltage-time product the device can  
withstand without saturating the transformer.  
In many cases, the same transformer could be used as either  
a pulse transformer operation or a gate drive transformer. In  
0, the major difference between the two applications is in the  
current waveforms. With a constant drive voltage and  
magnetizing inductance, LMAG, the magnetizing current IMAG  
is the same in both circuits. In the pulse transformer  
waveforms shown in 0(a), the resistor current IR follows the  
secondary voltage VS, and the driver supplies a current that  
is the sum of these two components. In the MOSFET gate  
drive waveforms shown in 0(b),  
Figure 8. Simplified Pulse Transformer Circuit  
In Figure 9, the circuit is modified so that the resistor is  
replaced by the gate-to-source terminal of a MOSFET  
located on the high side of a bridge circuit.  
+Bulk  
the gate current IG is positive pulses at turn on and negative  
pulses at turn off. As in the first example, the driver  
supplies a current that is the sum of these two components,  
but the waveform has a larger RMS value due to the high-  
current pulses.  
T1  
NP:NS  
VDD  
IDR  
IG  
+
VOUT  
-
CC  
+
VP  
-
+
VS  
-
IMAG  
It is important to examine the direction of current flow  
between driver and transformer for the examples of 0. When  
IN  
LMAG  
V
OUT swings high as shown Figure 11(a), one might expect  
the driver to immediately source current. However, the  
magnetizing current is negative and, if the load current is not  
larger than the magnetizing current, the driver must sink  
current until IDR goes positive. The opposite situation exists  
in Figure 11(b), when VOUT goes from high to low and the  
driver must source current when expected to operate as a  
current sink. Figure 11(c) shows additional diodes providing  
a current path if the driver cannot sink current when VOUT is  
high or source current when VOUT is low, as found in drivers  
with a bipolar output stage.  
Figure 9. Simplified Gate Drive Transformer Circuit  
0(a) shows the operational waveforms for the pulse  
transformer circuit, while 0(b) shows operation in a gate  
drive application.  
VOUT  
VOUT  
IDR  
IDR  
Gate Transformer  
Pulse Transformer  
(a)  
(a)  
(b)  
Figure 10. (a) Pulse Transformer Waveforms and  
(b) Gate Drive Transformer Waveforms  
The output of the driver swings from 0V to VDD producing a  
DC component equal to VDD x duty cycle. If this voltage is  
(b)  
© 2007 Fairchild Semiconductor Corporation  
Rev. 1.0.3 • 1/6/10  
www.fairchildsemi.com  
5

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