HCMOS, 7.5x5mm, 2.85V SMD Oscillator
RoHS Compliant / Pꢁ Free
Model: F4300 SERIES
Rev. 2/25/2008
Page 1 of2
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FEATURES
• 2.85V Operation
• HCMOS Output
• Standby Function
• Tape and Reel (2,000 pcs. STD)
• PART ꢀUMbER SELECTIOꢀLearn More - Internet Required
7.5 M ax
Model
Frequency
Stability
±100PPM
±100PPM
±50PPM
±50PPM
±25PPM
±25PPM*
±20PPM*
Operating
Frequency
Temperature (ºC) Range (MHz)
Part Number
Number
#4
#1
#3
Top
487-Frequency-xxxxx
604-Frequency-xxxxx
488-Frequency-xxxxx
605-Frequency-xxxxx
473-Frequency-xxxxx
606-Frequency-xxxxx
489-Frequency-xxxxx
-10 ~ +70
-40 ~ +85
-10 ~ +70
-40 ~ +85
-10 ~ +70
-40 ~ +85
-10 ~ +70
1.544 ~ 80.000
1.544 ~ 80.000
1.544 ~ 80.000
1.544 ~ 80.000
1.544 ~ 80.000
1.544 ~ 80.000
1.544 ~ 80.000
F4300
F4300R
F4305
F4305R
F4306
F4306R
F4308
5.2 M ax
View
#2
Dot denotes
pin 1
1.5 M ax
• ELECTRICAL CHARACTERISTICS
1.4±0.2
MAX (unless otherwise noted)
1.544 ~ 80.000 MHz
-55ºC ~ +125ºC
PARAMETERS
Frequency Range (Fo)
Temperature Range (Tstg)
#1
#4
#2
#3
Bottom
View
2.6±0.2
2.85V ± 5%
Supply Voltage
Input Current
(Vdd)
(Idd)
5.08±0.1
15mA
20mA
25mA
1.544 ~ 32.000 MHz
32.000+ ~ 50.000 MHz
50.000+ ~ 67.000 MHz
67.000+ ~ 80.000 MHz
Output Symmetry (50% Vdd)
Rise Time (10% ~ 90% Vdd) (Tr)
1.544 ~ 50.000 MHz
Recommended
Solder Pad Layout
30mA
45% ~ 55%
1.8±0.1
6nS
4nS
2.0±0.1
50.000 ~ 80.000 MHz
4.2±0.1
Fall Time (90% ~ 10% Vdd) (Tf)
1.544 ~ 50.000 MHz
6nS
4nS
10% Vdd
90% Vdd Min
2mA
50.000 ~ 80.000 MHz
5.08±0.1
Output Voltage
(Iol = 2mA) (Vol)
(Ioh = 2mA) (Voh)
(Vol = 10% Vdd) (Iol)
(Voh = 90% Vdd) (Ioh)
(HCMOS)
Output Current
Pin Connections
-2mA
15pF
10µA
10mS
150nS
10mS
#1 E/D
#2 G ND #4 VDD
#3 O utput
Output Load
Standby Current
Start-up Time
All dim ensions are in m illim eters
(Ts)
Output Disable Time 2
Output Enable Time 2
1 Inclusive of 25ºC tolerance, operating temperature range, input voltage change, load change, aging,
shock, and vibration. *Excludes Shock/Vibration
2 An internal pullup resistor from pin 1 to pin 4 allows active output if pin 1 is left open.
Note: A 0.01µF bypass capacitor should be placed between VDD (Pin 4) and GND (Pin 2) to
minimize power supply line noise.
Drawing is for reference to critical specifications defined by size measurements.
Certain non-critical visual attributes, such as side castellations, reference pin shape, etc. may
vary. All specifications subject to change without notice.
• EꢀAbLE / DISAbLE FUꢀCTIOꢀ
INH (Pin 1)
OUTPUT (Pin 3)
ACTIVE
OPEN 2
'1' Level VIh ≥ 70% Vdd
'0' Level VIl ≤ 30% Vdd
ACTIVE
High Z
FOXElectronics 5570 Enterprise Parkway Fort Myers, Florida 33905 USA +1.239.693.0099 FAX +1.239.693.1554 http://www.foxonline.com
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