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EVAL-ADN4654EB1Z

更新时间: 2024-02-03 05:49:15
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亚德诺 - ADI /
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25页 732K
描述
5 kV RMS and 3.75 kV RMS, Dual-Channel LVDS Gigabit Isolators

EVAL-ADN4654EB1Z 数据手册

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5 kV RMS and 3.75 kV RMS,  
Dual-Channel LVDS Gigabit Isolators  
Data Sheet  
ADN4654/ADN4655/ADN4656  
FEATURES  
FUNCTIONAL BLOCK DIAGRAMS  
V
V
IN1  
IN2  
5 kV rms and 3.75 kV rms LVDS isolators  
Complies with TIA/EIA-644-A LVDS standard  
Multiple dual-channel configurations  
Any data rate up to 1.1 Gbps switching with low jitter  
4 ns typical propagation delay  
ADN4654  
ISOLATION  
BARRIER  
LDO  
LDO  
V
D
V
DD2  
DD1  
D
D
IN1+  
IN1–  
OUT1+  
OUT1–  
D
2.6 ps rms typical random jitter, rms  
LVDS  
DIGITAL ISOLATOR  
LVDS  
90 ps typical peak-to-peak total jitter at 1.1 Gbps  
2.5 V or 3.3 V supplies  
D
D
D
D
IN2+  
OUT2+  
OUT2–  
IN2–  
−75 dBc power supply ripple rejection, phase spur level  
Glitch immunity  
GND  
GND  
2
1
8 kV IEC 61000-4-2 ESD protection across isolation barrier  
High common-mode transient immunity: >25 kV/μs  
Passes EN 55022 Class B radiated emissions limits with  
1.1 Gbps PRBS  
Safety and regulatory approvals (20-lead SOIC_W package)  
UL (pending): 5000 V rms for 1 minute per UL 1577  
CSA Component Acceptance Notice 5A (pending)  
VDE certificate of conformity (pending)  
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12  
Figure 1.  
V
V
IN2  
IN1  
ADN4655  
ISOLATION  
BARRIER  
LDO  
LDO  
V
D
V
DD2  
DD1  
D
D
IN1+  
IN1–  
OUT1+  
OUT1–  
D
LVDS  
DIGITAL ISOLATOR  
LVDS  
D
D
D
D
OUT2+  
IN2+  
IN2–  
OUT2–  
V
IORM = 424 VPEAK  
Fail-safe output high for open, short, and terminated input  
conditions (ADN4655/ADN4656)  
GND  
1
GND  
2
Figure 2.  
Operating temperature range: −40°C to +125°C  
7.8 mm minimum creepage and clearance  
V
V
IN1  
IN2  
ADN4656  
ISOLATION  
BARRIER  
LDO  
LDO  
APPLICATIONS  
V
V
DD1  
DD2  
Isolated video and imaging data  
Analog front-end isolation  
D
D
D
IN1+  
OUT1+  
D
OUT1–  
IN1–  
LVDS  
DIGITAL ISOLATOR  
LVDS  
Data plane isolation  
Isolated high speed clock and data links  
D
D
D
OUT2+  
IN2+  
D
OUT2–  
IN2–  
GND  
GND  
2
1
Figure 3.  
GENERAL DESCRIPTION  
The ADN4654/ADN4655/ADN46561 are signal isolated, low  
voltage differential signaling (LVDS) buffers that operate at up  
to 1.1 Gbps with low jitter. The devices integrate Analog Devices,  
Inc., iCoupler® technology, enhanced for high speed operation to  
provide galvanic isolation of the TIA/EIA-644-A compliant LVDS  
drivers and receivers. This integration allows drop-in isolation of  
an LVDS signal chain.  
the corresponding LVDS driver output when the inputs are  
floating, shorted, or terminated but not driven.  
For high speed operation with low jitter, the LVDS and isolator  
circuits rely on a 2.5 V supply. An integrated on-chip low dropout  
(LDO) regulator can provide the required 2.5 V from an external  
3.3 V power supply. The devices are fully specified over a wide  
industrial temperature range and come in a 20-lead, wide body  
SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP  
package with 3.75 kV rms isolation.  
The ADN4654/ADN4655/ADN4656 comprise multiple channel  
configurations, and the LVDS receivers on the ADN4655 and  
ADN4656 include a fail-safe mechanism to ensure a Logic 1 on  
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.  
Rev. C Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2018–2019 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 

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