100 MHz to 1000 MHz
Integrated Broadband Receiver
ADRF6850
FEATURES
GENERAL DESCRIPTION
IQ quadrature demodulator
Integrated fractional-N PLL and VCO
Gain control range: 60 dB
The ADRF6850 is a highly integrated broadband quadrature
demodulator, frequency synthesizer, and variable gain amplifier
(VGA). The device covers an operating frequency range from
100 MHz to 1000 MHz for use in both narrow-band and wideband
communications applications, performing quadrature demodu-
lation from IF directly to baseband frequencies.
Input frequency range: 100 MHz to 1000 MHz
Input P1dB: +12 dBm at 0 dB gain
Input IP3: +22.5 dBm at 0 dB gain
Noise figure: 11 dB at >39 dB gain, 49 dB at 0 dB gain
Baseband 1 dB bandwidth: 250 MHz in wideband mode,
50 MHz in narrow-band mode
The ADRF6850 demodulator includes a high modulus
fractional-N frequency synthesizer with integrated VCO,
providing better than 1 Hz frequency resolution, and a 60 dB
gain control range provided by a front-end VGA.
SPI/I2C serial interface
Power supply: +3.3 V/350 mA
Control of all the on-chip registers is through a user-selected
SPI interface or I2C interface. The device operates from a single
power supply ranging from 3.15 V to 3.45 V.
APPLICATIONS
Broadband communications
Cellular communications
Satellite communications
FUNCTIONAL BLOCK DIAGRAM
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
LOMON
LOMON
IBB
IBB
CCOMP1
CCOMP2
CCOMP3
60dB
GAIN CONTROL
RANGE
RFI
RFI
DRIVER
RFDIV
0°/90°
VCO
CORE
VTUNE
VOCM
RFCM
SEQUENCED
GAIN
INTERFACE
QBB
QBB
VGAIN
R
SET
REFERENCE
×2
5-BIT
DIVIDER
÷2
+
REFIN
DOUBLER
PHASE
CHARGE
PUMP
FREQUENCY
DETECTOR
CP
–
LF3
CURRENT SETTING
LF2
N-COUNTER
LDET
TESTLO
TESTLO
THIRD-ORDER
SDI/SDA
CLK/SCL
SDO
RFCP4 RFCP3 RFCP2 RFCP1
FRACTIONAL
SPI/
INTERPOLATOR
2
I C
INTERFACE
CS
FRACTIONAL
REGISTER
MODULUS
INTEGER
REGISTER
25
2
ADRF6850
GND
MUXOUT
Figure 1.
Rev. 0
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