Datasheet > EVAL-ADF7021DBZ2

EVAL-ADF7021DBZ2

更新时间： 2022-02-26 11:08:58

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
64页	1250K
描述
High Performance Narrow-Band Transceiver IC

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EVAL-ADF7021DBZ2 数据手册

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Data Sheet

ADF7021

ANALOG_TEST_

MODES

PLL_TEST_

MODES

Σ-Δ_TEST_

MODES

Tx_TEST_

MODES

Rx_TEST_

MODES

ADDRESS

BITS

CLK_-MUX

CAL OVERRIDE

AUTO CAL

OVERRIDE GAIN

OVERRIDE BW

PFD/CP TEST MODES

DEFAULT, NO BLEED

(+VE) CONSTANT BLEED

(–VE) CONSTANT BLEED

(–VE) PULSED BLEED

(–VE) PULSE BLD, DELAY UP?

CP PUMP UP

OVERRIDE BW AND GAIN

REG1 PD

NORMAL

PWR DWN

CP TRI-STATE

CP PUMP DN

FORCE LD HIGH

Σ-Δ TEST MODES

NORMAL

FORCE

DEFAULT, 3RD ORDER SD, NO DITHER

1ST ORDER SD

2ND ORDER SD

DITHER TO FIRST STAGE

DITHER TO SECOND STAGE

DITHER TO THIRD STAGE

DITHER × 8

ANALOG TEST MODES

BAND GAP VOLTGE

40µA CURRENT FROM REG4

FILTER I CHANNEL: STAGE 1

FILTER I CHANNEL: STAGE 2

FILTER I CHANNEL: STAGE 1

FILTER Q CHANNEL: STAGE 1

FILTER Q CHANNEL: STAGE 2

FILTER Q CHANNEL: STAGE 1

ADC REFERENCE VOLTAGE

BIAS CURRENT FROM RSSI 5µA

DITHER × 32

Tx TEST MODES

NORMAL OPERATION

Tx CARRIER ONLY

Tx +VE TONE ONLY

Tx –VE TONE ONLY

Tx "1010" PATTERN

Tx PN9 DATA, AT PROGRAMED RATE

Tx SYNC BYTE REPEATEDLY

10 FILTER COARSE CAL OSCILLATOR O/P

11 ANALOG RSSI I CHANNEL

12 OSET LOOP +VE FBACK V (I CH)

13 SUMMED O/P OF RSSI RECTIFIER+

14 SUMMED O/P OF RSSI RECTIFIER–

15 BIAS CURRENT FROM BB FILTER

Rx TEST MODES

NORMAL

SCLK, SDATA -> I, Q

REVERSE I,Q

I,Q TO TxRxCLK, TxRxDATA

3FSK SLICER ON TxRxDATA

CORRELATOR SLICER ON TxRxDATA

LINEAR SLICER ON RXDATA

SDATA TO CDR

PLL TEST MODES

NORMAL OPERATION

R DIV

N DIV

RCNTR/2 ON MUXOUT

NCNTR/2 ON MUXOUT

ACNTR TO MUXOUT

PFD PUMP UP TO MUXOUT

PFD PUMP DN TO MUXOUT

SDATA TO MUXOUT (OR SREAD?)

ADDITIONAL FILTERING ON I, Q

ENABLE REG 14 DEMOD PARAMETERS

10 POWER DOWN DDT AND ED IN T/4 MODE

11 ENVELOPE DETECTOR WATCHDOG DISABLED

12 RESERVED

13 PROHIBIT CALACTIVE

14 FORCE CALACTIVE

ANALOG LOCK DETECT ON MUXOUT

10 END OF COARSE CAL ON MUXOUT

11 END OF FINE CAL ON MUXOUT

FORCE NEW PRESCALER CONFIG.

FOR ALL N

15 ENABLE DEMOD DURING CAL

13 TEST MUX SELECTS DATA

14 LOCK DETECT PERCISION

15 RESERVED

CLK MUXES on CLKOUT pin

NORMAL, NO OUTPUT

DEMOD CLK

CDR CLK

SEQ CLK

BB OFFSET CLK

SIGMA DELTA CLK

ADC CLK

TxRxCLK

Figure 77. Register 15—Test Mode Register Map

Rev. B | Page 61 of 64

1...58 59 606162 63 64

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