EPF10K100ABC356-3

更新时间： 2024-01-15 18:43:13

品牌	Logo	应用领域
阿尔特拉 - ALTERA		可编程逻辑器件
页数	文件大小	规格书
128页	1953K
描述
Embedded Programmable Logic Device Family

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中文翻译

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数据手册
替代型号

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet

For more information, see the following documents:

■

Configuration Devices for APEX & FLEX Devices Data Sheet

BitBlaster Serial Download Cable Data Sheet

ByteBlasterMV Parallel Port Download Cable Data Sheet

Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000

Devices)

FLEX 10K devices are supported by Altera development systems; single,

integrated packages that offer schematic, text (including AHDL), and

waveform design entry, compilation and logic synthesis, full simulation

and worst-case timing analysis, and device configuration. The Altera

software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and

other interfaces for additional design entry and simulation support from

other industry-standard PC- and UNIX workstation-based EDA tools.

The Altera software works easily with common gate array EDA tools for

synthesis and simulation. For example, the Altera software can generate

Verilog HDL files for simulation with tools such as Cadence Verilog-XL.

Additionally, the Altera software contains EDA libraries that use device-

specific features such as carry chains which are used for fast counter and

arithmetic functions. For instance, the Synopsys Design Compiler library

supplied with the Altera development systems include DesignWare

functions that are optimized for the FLEX 10K architecture.

The Altera development systems run on Windows-based PCs and Sun

SPARCstation, and HP 9000 Series 700/800 workstations.

See the MAX+PLUS II Programmable Logic Development System & Software

Data Sheet for more information.

Functional

Each FLEX 10K device contains an embedded array to implement

memory and specialized logic functions, and a logic array to implement

general logic.

Description

The embedded array consists of a series of EABs. When implementing

memory functions, each EAB provides 2,048 bits, which can be used to

create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.

When implementing logic, each EAB can contribute 100 to 600 gates

towards complex logic functions, such as multipliers, microcontrollers,

state machines, and DSP functions. EABs can be used independently, or

multiple EABs can be combined to implement larger functions.

Altera Corporation

1...4 5 678 9 10...128

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EPF10K100ABC356-3 替代型号

型号	品牌	替代类型	描述	数据表
EPF10K100ABI356-3N	ALTERA	完全替代	Loadable PLD, 0.8ns, CMOS, PBGA356, BGA-356

与EPF10K100ABC356-3相关器件

型号	品牌	获取价格	描述	数据表
EPF10K100ABC356-3N	ALTERA	获取价格	Loadable PLD, 0.8ns, CMOS, PBGA356, BGA-356
EPF10K100ABC600-1	ALTERA	获取价格	Loadable PLD, 0.6ns, CMOS, PBGA600, BGA-600
EPF10K100ABC600-2N	INTEL	获取价格	Loadable PLD, 0.7ns, CMOS, PBGA600, BGA-600
EPF10K100ABC600-3	INTEL	获取价格	Loadable PLD, 0.8ns, CMOS, PBGA600, BGA-600
EPF10K100ABC600-3	ALTERA	获取价格	Loadable PLD, 0.8ns, CMOS, PBGA600, BGA-600
EPF10K100ABI356-2	INTEL	获取价格	Loadable PLD, 0.7ns, CMOS, PBGA356, BGA-356
EPF10K100ABI356-2N	INTEL	获取价格	Loadable PLD, 0.7ns, CMOS, PBGA356, BGA-356
EPF10K100ABI356-3	INTEL	获取价格	Loadable PLD, 0.8ns, CMOS, PBGA356, BGA-356
EPF10K100ABI356-3N	ALTERA	获取价格	Loadable PLD, 0.8ns, CMOS, PBGA356, BGA-356
EPF10K100ABI356-3N	INTEL	获取价格	Loadable PLD, 0.8ns, CMOS, PBGA356, BGA-356

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