Datasheet > EP2AGX65EF29C6N

EP2AGX65EF29C6N

更新时间： 2024-01-25 00:33:07

品牌	Logo	应用领域
英特尔 - INTEL		时钟 LTE 栅可编程逻辑
页数	文件大小	规格书
78页	808K
描述
Field Programmable Gate Array, 500MHz, PBGA780, 29 X 29 MM, LEAD FREE, MS-034, FBGA-780

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EP2AGX65EF29C6N 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	HBGA,	Reach Compliance Code：	compliant
风险等级：	5.27	最大时钟频率：	500 MHz
JESD-30 代码：	S-PBGA-B780	JESD-609代码：	e1
长度：	29 mm	端子数量：	780
最高工作温度：	85 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	HBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, HEAT SINK/SLUG
峰值回流温度（摄氏度）：	NOT SPECIFIED	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
座面最大高度：	2.7 mm	最大供电电压：	0.93 V
最小供电电压：	0.87 V	标称供电电压：	0.9 V
表面贴装：	YES	温度等级：	OTHER
端子面层：	TIN SILVER COPPER	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	29 mm
Base Number Matches：	1

EP2AGX65EF29C6N 数据手册

Chapter 1: Device Datasheet for Arria II Devices

1–7

Electrical Characteristics

Table 1–6. Recommended Operating Conditions for Arria II GZ Devices (Note 6) (Part 2 of 2)

Symbol

Description

Condition

Minimum

Typical

Maximum Unit

V_{CCL_GXBLn}

(3)

Transceiver clock power (left side)

—

1.05

1.1

1.15

V_{CCL_GXBRn}

(3)

Transceiver clock power (right side)

—

1.05

1.1

V_{CCH_GXBLn}

(3)

Transmitter output buffer power (left side)

Transmitter output buffer power (right side)

1.33/1.425 1.4/1.5 (5)

1.575

V_{CCH_GXBRn}

(3)

Commercial

Industrial

—

°C

T_J

Operating junction temperature

Power supply ramp time

–40

100

Normal POR

(PORSEL=0)

0.05

—

100

t_RAMP

Fast POR

(PORSEL=1)

Notes to Table 1–6:

(1) Altera recommends a 3.0-V nominal battery voltage when connecting V_CCBATto a battery for volatile key backup. If you do not use the volatile

security key, you may connect the V_CCBATto either GND or a 3.0-V power supply.

(2) V_CCPDmust be 2.5 V when V_CCIOis 2.5, 1.8, 1.5, or 1.2 V. V_CCPDmust be 3.0 V when V_CCIOis 3.0 V.

(3) n = 0, 1, or 2.

(4) V_{CCA_L/R}must be connected to a 3.0-V supply if the clock multiplier unit (CMU) phase-locked loop (PLL), receiver clock data recovery (CDR), or

both, are configured at a base data rate > 4.25 Gbps. For data rates up to 4.25 Gbps, you can connect V_{CCA_L/R}to either 3.0 V or 2.5 V.

(5) V_{CCH_GXBL/R}must be connected to a 1.4-V supply if the transmitter channel data rate is > 6.5 Gbps. For data rates up to 6.5 Gbps, you can connect

_{CCH_GXBL/R}to either 1.4 V or 1.5 V.

(6) Transceiver power supplies do not have power-on-reset (POR) circuitry. After initial power-up, violating the transceiver power supply operating

conditions could lead to unpredictable link behavior.

DC Characteristics

This section lists the supply current, I/O pin leakage current, on-chip termination

(OCT) accuracy and variation, input pin capacitance, internal weak pull-up and

pull-down resistance, hot socketing, and Schmitt trigger input specifications.

Supply Current

Standby current is the current the device draws after the device is configured with no

inputs or outputs toggling and no activity in the device. Because these currents vary

largely with the resources used, use the Microsoft Excel-based Early Power Estimator

(EPE) to get supply current estimates for your design.

For more information about power estimation tools, refer to the PowerPlay Early Power

Estimator User Guide and the PowerPlay Power Analysis chapter.

December 2013 Altera Corporation

Arria II Device Handbook Volume 3: Device Datasheet and Addendum

1...4 5 678 9 10...78

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EP2AGX65EU17I5N	INTEL	Field Programmable Gate Array, 500MHz, PBGA358, 17 X 17 MM, LEAD FREE, MO-275, UBGA-358	获取价格

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