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EP2AGX65EF25I3N PDF预览

EP2AGX65EF25I3N

更新时间: 2024-02-03 18:34:32
品牌 Logo 应用领域
英特尔 - INTEL 时钟可编程逻辑
页数 文件大小 规格书
78页 808K
描述
Field Programmable Gate Array, 500MHz, PBGA572, 25 X 25 MM, LEAD FREE, MS-034, FBGA-572

EP2AGX65EF25I3N 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HBGA,Reach Compliance Code:compliant
风险等级:5.27最大时钟频率:500 MHz
JESD-30 代码:S-PBGA-B572JESD-609代码:e1
长度:25 mm端子数量:572
最高工作温度:100 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HBGA
封装形状:SQUARE封装形式:GRID ARRAY, HEAT SINK/SLUG
峰值回流温度(摄氏度):NOT SPECIFIED可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
座面最大高度:2.2 mm最大供电电压:0.93 V
最小供电电压:0.87 V标称供电电压:0.9 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:25 mm
Base Number Matches:1

EP2AGX65EF25I3N 数据手册

 浏览型号EP2AGX65EF25I3N的Datasheet PDF文件第72页浏览型号EP2AGX65EF25I3N的Datasheet PDF文件第73页浏览型号EP2AGX65EF25I3N的Datasheet PDF文件第74页浏览型号EP2AGX65EF25I3N的Datasheet PDF文件第75页浏览型号EP2AGX65EF25I3N的Datasheet PDF文件第76页浏览型号EP2AGX65EF25I3N的Datasheet PDF文件第77页 
1–78  
Chapter 1: Device Datasheet for Arria II Devices  
Document Revision History  
Table 1–69. Document Revision History (Part 2 of 2)  
Date  
Version  
Changes  
Added Arria II GZ information.  
Added Table 1–61 with Arria II GX information.  
Updated Table 1–1, Table 1–2, Table 1–5, Table 1–6, Table 1–7, Table 1–11, Table 1–35,  
Table 1–37, Table 1–40, Table 1–42, Table 1–44, Table 1–45, Table 1–57, Table 1–61, and  
Table 1–63.  
December 2010  
4.0  
Updated Figure 1–5.  
Updated for the Quartus II version 10.0 release.  
Updated the first paragraph for searchability.  
Minor text edits.  
Updated Table 1–1, Table 1–4, Table 1–16, Table 1–19, Table 1–21, Table 1–23,  
Table 1–25, Table 1–26, Table 1–30, and Table 1–35  
Added Table 1–27 and Table 1–29.  
Added I3 speed grade information to Table 1–19, Table 1–21, Table 1–22, Table 1–24,  
Table 1–25, Table 1–30, Table 1–32, Table 1–33, Table 1–34, and Table 1–35.  
July 2010  
3.0  
Updated the “Operating Conditions” section.  
Removed “Preliminary” from Table 1–19, Table 1–21, Table 1–22, Table 1–23,  
Table 1–24, Table 1–25, Table 1–26, Table 1–28, Table 1–30, Table 1–32, Table 1–33,  
Table 1–34, and Figure 1–4.  
Minor text edits.  
Updated for the Quartus II version 9.1 SP2 release:  
Updated Table 1–3, Table 1–7, Table 1–19, Table 1–21, Table 1–22, Table 1–24,  
Table 1–25 and Table 1–33.  
March 2010  
2.3  
Updated “Recommended Operating Conditions” section.  
Minor text edits.  
February 2010  
February 2010  
2.2  
2.1  
Updated Table 1–19.  
Updated for Arria II GX v9.1 SP1 release:  
Updated Table 1–19, Table 1–23, Table 1–28, Table 1–30, and Table 1–33.  
Added Figure 1–5.  
Minor text edits.  
Updated for Arria II GX v9.1 release:  
Updated Table 1–1, Table 1–4, Table 1–13, Table 1–14, Table 1–19, Table 1–15,  
Table 1–22, Table 1–24, and Table 1–28.  
Added Table 1–6 and Table 1–33.  
Added “Bus Hold” on page 1–5.  
Added “IOE Programmable Delay” section.  
Minor text edit.  
November 2009  
2.0  
1.2  
Updated Table 1–1, Table 1–3, Table 1–7, Table 1–8, Table 1–18, Table 1–23, Table 1–25,  
Table 1–26, Table 1–29, Table 1–30, Table 1–31, Table 1–32, and Table 1–33.  
June 2009  
Added Table 1–32.  
Updated Equation 1–1.  
Added “I/O Timing” section.  
Initial release.  
March 2009  
1.1  
1.0  
February 2009  
Arria II Device Handbook Volume 3: Device Datasheet and Addendum  
December 2013 Altera Corporation  

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