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EP20K100ERI208-3X PDF预览

EP20K100ERI208-3X

更新时间: 2023-02-15 00:00:00
品牌 Logo 应用领域
阿尔特拉 - ALTERA /
页数 文件大小 规格书
116页 1588K
描述
Loadable PLD, CMOS, PQFP208, 30.40 X 30.40 MM, 0.50 MM PITCH, RQFP-208

EP20K100ERI208-3X 数据手册

 浏览型号EP20K100ERI208-3X的Datasheet PDF文件第3页浏览型号EP20K100ERI208-3X的Datasheet PDF文件第4页浏览型号EP20K100ERI208-3X的Datasheet PDF文件第5页浏览型号EP20K100ERI208-3X的Datasheet PDF文件第7页浏览型号EP20K100ERI208-3X的Datasheet PDF文件第8页浏览型号EP20K100ERI208-3X的Datasheet PDF文件第9页 
APEX 20K Programmable Logic Device Family Data Sheet  
APEXTM 20K devices are the first PLDs designed with the MultiCore  
General  
Description  
architecture, which combines the strengths of LUT-based and product-  
term-based devices with an enhanced memory structure. LUT-based logic  
provides optimized performance and efficiency for data-path, register-  
intensive, mathematical, or digital signal processing (DSP) designs.  
Product-term-based logic is optimized for complex combinatorial paths,  
such as complex state machines. LUT- and product-term-based logic  
combined with memory functions and a wide variety of MegaCore and  
AMPP functions make the APEX 20K device architecture uniquely suited  
for system-on-a-programmable-chip designs. Applications historically  
requiring a combination of LUT-, product-term-, and memory-based  
devices can now be integrated into one APEX 20K device.  
APEX 20KE devices are a superset of APEX 20K devices and include  
additional features such as advanced I/ O standard support, CAM,  
additional global clocks, and enhanced ClockLock clock circuitry. In  
addition, APEX 20KE devices extend the APEX 20K family to 1.5 million  
gates. APEX 20KE devices are denoted with an “E” suffix in the device  
name (e.g., the EP20K1000E device is an APEX 20KE device). Table 8  
compares the features included in APEX 20K and APEX 20KE devices.  
6
Altera Corporation  

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