Datasheet > EM7180SFP01B

EM7180SFP01B

更新时间： 2022-02-26 13:08:18

品牌	Logo	应用领域
EMMICRO		/
页数	文件大小	规格书
18页	1158K
描述
Ultra Low Power Sensor Fusion Platform

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EM7180SFP01B 数据手册

EM7180SFP

Once setting of ODR and EventEnable register is completed, Host MCU can enable Normal Operation by setting bit

Run Request in HostControl register (writing 0x01 into the register). This would also clear initial Host_int (set after

completion of configuration file upload).

Example steps to enter Normal Operation are given below:

Write 0x1E0A0F to the MagRate register. Since SENtral automatically increments to the next register, this also

populates the AccelRate and GyroRate registers. This sets MagRate to 30 Hz, AccelRate to 100 Hz, and GyroRate to

150 Hz.

Write 0x01 to the QRateDivisor Register. This sets the quaternion output data rate to equal the GyroRate. For writing

0x01 this step is optional, since the default also sets the quaternion output data rate equal to GyroRate.

Write 0x07 to the EnableEvents register. This sets up the host to receive interrupts from SENtral whenever the

quaternion results registers are updated, an error has been detected, or when SENtral needs to be reset.

After performing the steps listed above, SENtral is ready to start generating orientation data. Below are the steps to follow when

operating in Normal Operation state. Write 0x01 to the HostControl register. This sets the RunRequest bit to ‘1’ and enables the

sensors and the SENtral algorithm. Read the ActualMagRate, ActualAccelRate, and ActualGyroRate registers to ensure the

ODRs are as expected. If operating in an interrupt-driven mode, then the Host MCU waits until it receives an interrupt signal

from SENtral. Alternatively the host may operate on a polling basis, rather than an interrupt-driven basis, in which case the

interrupt line may not be used. Once an interrupt is received by the Host or the Host otherwise decides to read new data, read

the EventStatus register.

a) Interpret and act on the EventStatus register in the priority shown in Fig. 6. If bit [1], the Error bit, is ‘1’ or if bit [0],

the CPUReset bit, is ‘1’, see “Section Error and CPUReset”. If bits [2], [3], [4], or [5], the Results bits, are ‘1’, read

the desired data (see Section “Read Results”).

b) Repeat steps c – e until new orientation data is not needed and/or the host decides to enter a different state.

Reading the EventStatus register clears it. It is possible for more than one bit position to be ‘1’ in the EventStatus register,

especially if the host does not always read the EventStatus register after receiving an interrupt. Similarly, if multiple bits are set

to ‘1’ in the EventStatus register, once the register is read all the bits will be set to ‘0’. For this reason the EventStatus register

should be processed in the priority shown in Fig. 6, as information will be cleared for events that are not handled.

Fig. 6 SENtral Normal Operation Flow

www.emmicroelectronic.com

7180SFP-DS Version 1.1, 10-Dec-14

420005-A01, 2.0

1...4 5 678 9 10...18

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EM720F32-85LF	EMLSI	256K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM	获取价格
EM720F32-85LL	EMLSI	256K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM	获取价格
EM720F32B-45LF	EMLSI	256K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM	获取价格
EM720F32B-45LL	EMLSI	256K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM	获取价格

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