Datasheet > EM68C16CWQG-3IH

EM68C16CWQG-3IH

更新时间： 2022-02-26 12:34:35

品牌	Logo	应用领域
钰创 - ETRON		动态存储器双倍数据速率
页数	文件大小	规格书
60页	1276K
描述
64M x 16 bit DDRII Synchronous DRAM (SDRAM)

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EM68C16CWQG-3IH 数据手册

EtronTech

EM68C16CWQG

Figure 3. State Diagram

CKEL

OCD

Initialization

calibration

Sequence

Self

Refreshing

Setting

MR,

Idle

All banks

precharged

(E)MRS

REF

EMR(1)

EMR(2)

EMR(3)

Refreshing

ACT

Precharge

Power

Down

Automatic Sequence

Cammand Sequence

Activating

CKEL

Active

Power

Down

Bank

Active

Reading

Writing

CKEL = CKE LOW, enter Power Down

CKEH = CKE HIGH, exit Power Down,exit Self Refresh

ACT = Activate

RDA

WRA

WR(A) = Write (with Autoprecharge)

RD(A) = Read (with Autoprecharge)

PR(A) = Precharge (All)

Reading

With

Autoprecharge

PR, PRA

Writing

With

Autoprecharge

PR, PRA

(E)MRS = (Extended) Mode Register Set

SRF = Enter Self Refresh

Precharging

REF = Refresh

Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and the

commands to control them, not all details. In particular situations involving more than one bank,

enabling/disabling on-die termination, Power Down entry/exit, timing restrictions during state transitions, among

other things, are not captured in full detail.

Rev. 1.2

Apr. /2016

1 2 345 6 7...60

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