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EIA1616-8P-2 PDF预览

EIA1616-8P-2

更新时间: 2022-12-18 00:31:42
品牌 Logo 应用领域
EXCELICS /
页数 文件大小 规格书
2页 91K
描述
16.2-16.4GHz 8-Watt Internally Matched Power FET

EIA1616-8P-2 数据手册

 浏览型号EIA1616-8P-2的Datasheet PDF文件第2页 
EIA1616-8P-2  
UPDATED 11/09/06  
16.2-16.4GHz 8-Watt Internally Matched Power FET  
FEATURES  
16.2– 16.4GHz Bandwidth  
Input/Output Impedance Matched to 50 Ohms  
+39.0 dBm Output Power at 1dB Compression  
6.0 dB Min. Power Gain at 1dB Compression  
30% Power Added Efficiency  
EIA1616-8P-2  
Non-Hermetic Metal Flange Package  
100% Tested for DC, RF, and RTH  
Caution! ESD sensitive device.  
ELECTRICAL CHARACTERISTICS (Ta = 25°C)  
SYMBOL  
P1dB  
PARAMETERS/TEST CONDITIONS1  
MIN  
TYP  
MAX  
UNITS  
Output Power at 1dB Compression  
VDS = 8 V, IDSQ 2200mA  
Gain at 1dB Compression  
DS = 8 V, IDSQ 2200mA  
f = 16.2-16.4GHz  
f = 16.2-16.4GHz  
f = 16.2-16.4GHz  
38.0  
39.0  
dBm  
6.0  
7.0  
dB  
dB  
%
G1dB  
G  
V
Gain Flatness  
±0.6  
VDS = 8 V, IDSQ 2200mA  
Power Added Efficiency at 1dB Compression  
30  
PAE  
V
DS = 8 V, IDSQ 2200mA  
f = 16.2-16.4GHz  
Drain Current at 1dB Compression  
f = 16.2-16.4GHz  
2600  
4000  
-1.0  
3.5  
3200  
6000  
-2.5  
4.0  
mA  
mA  
V
Id1dB  
IDSS  
VP  
Saturated Drain Current  
Pinch-off Voltage  
VDS = 3 V, VGS = 0 V  
VDS = 3 V, IDS = 40 mA  
Thermal Resistance2  
oC/W  
RTH  
Note:  
1. Tested with 100 Ohm gate resistor.  
2. Overall Rth depends on case mounting.  
ABSOLUTE MAXIMUM RATING1,2  
SYMBOLS  
Vds  
Vgs  
Igf  
PARAMETERS  
Drain-Source Voltage  
ABSOLUTE1  
CONTINUOUS2  
8V  
-3V  
10V  
-5V  
Gate-Source Voltage  
Forward Gate Current  
Reverse Gate Current  
Input Power  
86.4mA  
-14.4mA  
38 dBm  
175 oC  
28.8mA  
-4.8mA  
Igr  
@ 3dB Compression  
175 oC  
Pin  
Channel Temperature  
Storage Temperature  
Total Power Dissipation  
Tch  
Tstg  
Pt  
-65 to +175 oC  
-65 to +175 oC  
38W  
38W  
Notes:  
1. Operating the device beyond any of the above ratings may result in permanent damage or reduction of MTTF.  
2.  
Bias conditions must also satisfy the following equation PT < (TCH –TPKG)/RTH; where TPKG = temperature of package,  
and PT = (VDS * IDS) – (POUT – PIN).  
Specifications are subject to change without notice.  
Excelics Semiconductor, Inc. 310 De Guigne Drive, Sunnyvale, CA 94085  
Phone: 408-737-1711 Fax: 408-737-1868 Web: www.excelics.com  
page 1 of 2  
Revised November 2006  

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