Datasheet > EBE21RD4AGFA

EBE21RD4AGFA

更新时间： 2022-11-25 10:59:10

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
23页	183K
描述
2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)

阅读下载

获取价格

如果您发现信息不准确，欢迎纠错

EBE21RD4AGFA 数据手册

EBE21RD4AGFA

Differential Clock Net Wiring (CK0, /CK0)

0ns (nominal)

SDRAM

PLL

120Ω

OUT1

120Ω

SDRAM

CK0

/CK0

120Ω

OUT'N'

Feedback in

Feedback out

120Ω

Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl

be set to 0ns (nominal).

2. Input, output and feedback clock lines are terminated from line to line as shown, and not

from line to ground.

3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired

in a similar manner.

4. Termination resistors for the PLL feedback path clocks are located as close to the

input pin of the PLL as possible.

Data Sheet E0794E20 (Ver. 2.0)

1...6 7 8910 11 12...23

下载PDF

型号	品牌	描述	获取价格	数据表
EBE21RD4AGFA-4A-E	ELPIDA	2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)	获取价格
EBE21RD4AGFA-5C-E	ELPIDA	2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)	获取价格
EBE21RD4AGFA-6E-E	ELPIDA	2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)	获取价格
EBE21RD4AGFB	ELPIDA	2GB Registered DDR2 SDRAM DIMM	获取价格
EBE21RD4AGFB-4A-E	ELPIDA	2GB Registered DDR2 SDRAM DIMM	获取价格
EBE21RD4AGFB-5C-E	ELPIDA	2GB Registered DDR2 SDRAM DIMM	获取价格