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EBE21RD4AEFA-4A-E PDF预览

EBE21RD4AEFA-4A-E

更新时间: 2024-02-20 20:03:53
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
22页 188K
描述
2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)

EBE21RD4AEFA-4A-E 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM240,40
针数:240Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84Is Samacsys:N
访问模式:DUAL BANK PAGE BURST最长访问时间:0.6 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N240
内存密度:19327352832 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:72功能数量:1
端口数量:1端子数量:240
字数:268435456 words字数代码:256000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:组织:256MX72
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM240,40
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):260电源:1.8 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES最大待机电流:0.81 A
子类别:DRAMs最大压摆率:6.85 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:NO
技术:CMOS温度等级:OTHER
端子形式:NO LEAD端子节距:1 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

EBE21RD4AEFA-4A-E 数据手册

 浏览型号EBE21RD4AEFA-4A-E的Datasheet PDF文件第2页浏览型号EBE21RD4AEFA-4A-E的Datasheet PDF文件第3页浏览型号EBE21RD4AEFA-4A-E的Datasheet PDF文件第4页浏览型号EBE21RD4AEFA-4A-E的Datasheet PDF文件第6页浏览型号EBE21RD4AEFA-4A-E的Datasheet PDF文件第7页浏览型号EBE21RD4AEFA-4A-E的Datasheet PDF文件第8页 
EBE21RD4AEFA  
Serial PD Matrix*1  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value  
Comments  
128 bytes  
Number of bytes utilized by module  
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H  
08H  
manufacturer  
Total number of bytes in serial PD  
device  
256 bytes  
2
3
4
5
6
7
8
Memory type  
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
1
0
0
1
08H  
0EH  
0BH  
61H  
48H  
00H  
05H  
DDR2 SDRAM  
Number of row address  
Number of column address  
Number of DIMM ranks  
Module data width  
14  
11  
2
72  
Module data width continuation  
Voltage interface level of this assembly  
0
SSTL 1.8V  
DDR SDRAM cycle time, CL = 5  
-5C  
9
0
0
0
0
1
1
1
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
0
0
3DH  
50H  
50H  
3.75ns*1  
5.0ns*1  
0.5ns*1  
-4A  
SDRAM access from clock (tAC)  
-5C  
10  
-4A  
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
60H  
02H  
82H  
04H  
04H  
00H  
0.6ns*1  
ECC  
7.8µs  
× 4  
11  
12  
13  
14  
15  
DIMM configuration type  
Refresh rate/type  
Primary SDRAM width  
Error checking SDRAM width  
Reserved  
× 4  
0
SDRAM device attributes:  
Burst length supported  
16  
17  
18  
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0CH  
04H  
38H  
4,8  
SDRAM device attributes: Number of  
banks on SDRAM device  
4
SDRAM device attributes:  
/CAS latency  
3, 4, 5  
19  
20  
21  
22  
Reserved  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
00H  
01H  
00H  
01H  
0
DIMM type information  
SDRAM module attributes  
SDRAM device attributes: General  
Registered  
Normal  
Weak Driver  
Minimum clock cycle time at CL = 4  
-5C  
23  
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
0
3DH  
50H  
3.75ns*1  
5.0ns*1  
-4A  
Maximum data access time (tAC) from  
clock at CL = 4  
-5C  
24  
0
1
0
1
0
0
0
0
50H  
0.5ns*1  
-4A  
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
60H  
50H  
0.6ns*1  
5.0ns*1  
25  
26  
27  
28  
29  
Minimum clock cycle time at CL = 3  
Maximum data access time (tAC) from  
clock at CL = 3  
0
0
0
0
1
0
0
0
1
1
0
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0
1
0
0
0
0
0
60H  
3CH  
1EH  
3CH  
0.6ns*1  
15ns  
Minimum row precharge time (tRP)  
Minimum row active to row active delay  
(tRRD)  
7.5ns  
15ns  
Minimum /RAS to /CAS delay (tRCD)  
Data Sheet E0671E20 (Ver. 2.0)  
5

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