EBE20RE4ABFA-4A-E

更新时间： 2024-02-03 07:44:00

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
29页	240K
描述
2GB Registered DDR2 SDRAM DIMM

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EBE20RE4ABFA-4A-E 数据手册

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EBE20RE4ABFA

Serial PD Matrix

Byte No. Function described

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

Number of bytes utilized by module

manufacturer

80H

08H

128 bytes

256 bytes

Total number of bytes in serial PD

device

Memory type

08H

0EH

0BH

60H

48H

00H

05H

DDR2 SDRAM

Number of row address

Number of column address

Number of DIMM ranks

Module data width

Module data width continuation

Voltage interface level of this assembly 0

SSTL 1.8V

DDR SDRAM cycle time, CL = 5

-6E

30H

3.0ns*¹

-5C

-4A

3DH

50H

3.75ns*¹

5.0ns*¹

SDRAM access from clock (tAC)

-6E

45H

0.45ns*¹

-5C

50H

60H

02H

82H

04H

00H

0.5ns*¹

0.6ns*¹

ECC

7.8µs

× 4

-4A

DIMM configuration type

Refresh rate/type

Primary SDRAM width

Error checking SDRAM width

Reserved

× 4

SDRAM device attributes:

Burst length supported

0CH

08H

38H

4,8

SDRAM device attributes: Number of

banks on SDRAM device

SDRAM device attributes:

/CAS latency

3, 4, 5

DIMM Mechanical Characteristics

DIMM type information

01H

00H

4.00mm max.

Registered

Normal

SDRAM module attributes

Weak Driver

50Ω ODT Support

SDRAM device attributes: General

03H

Minimum clock cycle time at CL = 4

-6E, -5C

3DH

50H

3.75ns*¹

5.0ns*¹

-4A

Maximum data access time (tAC) from

clock at CL = 4

50H

0.5ns*¹

-6E, -5C

-4A

60H

50H

0.6ns*¹

5.0ns*¹

Minimum clock cycle time at CL = 3

Maximum data access time (tAC) from

clock at CL = 3

60H

3CH

1EH

3CH

0.6ns*¹

15ns

Minimum row precharge time (tRP)

Minimum row active to row active delay

(tRRD)

7.5ns

15ns

Minimum /RAS to /CAS delay (tRCD)

Data Sheet E0873E40 (Ver. 4.0)

1 2 3 456 7 8...29

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