Datasheet > EBE20AE4ABFA

EBE20AE4ABFA

更新时间： 2022-12-22 00:39:56

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
27页	224K
描述
2GB Registered DDR2 SDRAM DIMM

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EBE20AE4ABFA 数据手册

EBE20AE4ABFA

Serial PD Matrix

Byte No. Function described

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

Number of bytes utilized by module

manufacturer

80H

08H

128 bytes

256 bytes

Total number of bytes in serial PD

device

Memory type

08H

0EH

0BH

60H

48H

00H

DDR2 SDRAM

Number of row address

Number of column address

Number of DIMM ranks

Module data width

Module data width continuation

Voltage interface level of this

assembly

05H

SSTL 1.8V

DDR SDRAM cycle time, CL = 5

SDRAM access from clock (tAC)

30H

45H

3.0ns*¹

0.45ns*¹

ECC, Address/

DIMM configuration type

06H

Command Parity

Refresh rate/type

82H

04H

00H

7.8µs

× 4

Primary SDRAM width

Error checking SDRAM width

Reserved

SDRAM device attributes:

Burst length supported

0CH

08H

38H

4,8

SDRAM device attributes: Number

of banks on SDRAM device

SDRAM device attributes:

/CAS latency

3, 4, 5

DIMM Mechanical Characteristics

DIMM type information

01H

00H

4.00mm max.

Registered

Normal

SDRAM module attributes

Weak Driver

50Ω ODT Support

SDRAM device attributes: General 0

Minimum clock cycle time at CL = 4 0

03H

3DH

50H

60H

3CH

1EH

3.75ns*¹

0.5ns*¹

5.0ns*¹

0.6ns*¹

15ns

Maximum data access time (tAC)

from clock at CL = 4

Minimum clock cycle time at CL = 3 0

Maximum data access time (tAC)

from clock at CL = 3

Minimum row precharge time (tRP)

Minimum row active to row active

delay (tRRD)

7.5ns

Minimum /RAS to /CAS delay

(tRCD)

3CH

15ns

Minimum active to precharge time

(tRAS)

2DH

02H

20H

45ns

Module rank density

2GB

Address and command setup time

before clock (tIS)

0.20ns*¹

Address and command hold time

after clock (tIH)

27H

10H

0.27ns*¹

0.10ns*¹

Data input setup time before clock

(tDS)

Data Sheet E0875E30 (Ver. 3.0)

1 2 3 456 7 8...27

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