Datasheet > EBE20RE4AAFA

EBE20RE4AAFA

更新时间： 2022-11-25 10:32:54

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
22页	187K
描述
2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank)

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

EBE20RE4AAFA 数据手册

DATA SHEET

2GB Registered DDR2 SDRAM DIMM

EBE20RE4AAFA (256M words × 72 bits, 1 Rank)

Description

Features

The EBE20RE4AAFA is a 256M words × 72 bits, 1

rank DDR2 SDRAM Module, mounting 18 pieces of

DDR2 SDRAM sealed in FBGA (µBGA^) package.

Read and write operations are performed at the cross

points of the CK and the /CK. This high-speed data

transfer is realized by the 4bits prefetch-pipelined

architecture. Data strobe (DQS and /DQS) both for

read and write are available for high speed and reliable

data bus design. By setting extended mode register,

the on-chip Delay Locked Loop (DLL) can be set

enable or disable. This module provides high density

mounting without utilizing surface mount technology.

Decoupling capacitors are mounted beside each FBGA

(µBGA) on the module board.

• 240-pin socket type dual in line memory module

(DIMM)

PCB height: 30.0mm

Lead pitch: 1.0mm

Lead-free

• Power supply: VDD, VDDQ = 1.8V ± 0.1V

• Data rate: 533Mbps/400Mbps (max.)

• SSTL_18 compatible I/O

• Double-data-rate architecture: two data transfers per

clock cycle

• Bi-directional, data strobe (DQS and /DQS) is

transmitted /received with data, to be used in

capturing data at the receiver

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

Note: Do not push the components or drop the

modules in order to avoid mechanical defects,

which may result in electrical defects.

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Eight internal banks for concurrent operation

(Component)

• Burst length: 4, 8

• /CAS latency (CL): 3, 4, 5

• Auto precharge option for each burst access

• Auto refresh and self refresh modes

• Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe

operation

• 1 piece of PLL clock driver, 2 pieces of register driver

and 1 piece of serial EEPROM (2k bits EEPROM) for

Presence Detect (PD)

Document No. E0440E30 (Ver. 3.0)

Date Published March 2005 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2003-2005

12 3 4 5 6 7...22

下载PDF

与EBE20RE4AAFA相关器件

型号	品牌	描述	获取价格	数据表
EBE20RE4AAFA-4A-E	ELPIDA	2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank)	获取价格
EBE20RE4AAFA-5C-E	ELPIDA	2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank)	获取价格
EBE20RE4ABFA	ELPIDA	2GB Registered DDR2 SDRAM DIMM	获取价格
EBE20RE4ABFA-4A-E	ELPIDA	2GB Registered DDR2 SDRAM DIMM	获取价格
EBE20RE4ABFA-5C-E	ELPIDA	2GB Registered DDR2 SDRAM DIMM	获取价格
EBE20RE4ABFA-6E-E	ELPIDA	2GB Registered DDR2 SDRAM DIMM	获取价格