EBE11FD8AGFD-6E-E

更新时间： 2024-02-04 00:56:55

品牌	Logo	应用领域
尔必达 - ELPIDA		/
页数	文件大小	规格书
22页	189K
描述
1GB Fully Buffered DIMM

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数据手册

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EBE11FD8AGFD-6E-E 数据手册

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EBE11FD8AGFD, EBE11FD8AGFN

Advanced Memory Buffer Block Diagram

Southbound

Data in

Southbound

Data out

10×2

Reference

clock

Data merge

PLL

RE-time

Re-synch

1×2

Demux

PISO

/RESET

Reset

control

10×12

Link init SM

and control

and CSRs

Init

patterns

Thermal

sensor

Mux

IBIST-RX

LAI logic

DRAM Command

IBIST-TX

DRAM clock

failover

Command

decoder &

CRC check

Command

out

DRAM

address and

command copy1

Mux

DRAM

interface

DDR state controller

and CSRs

DRAM

address and

command copy2

Core

controller

and CSRs

Write data

FIFO

Data out

Data in

72+18×2

DRAM

data and strobes

External MemBIST

DDR calibration

Sync & idle

pattern

generator

Data CRC

generator and

Read FIFO

NB LAI Buffer

IBIST-TX IBIST-RX

LAI

controller

Link init SM

and control

and CSRs

Mux

SMBus

failover

SMBus

14×6×2

14×12

controller

PISO

Demux

Re-synch

RE-time

Data merge

Northbound

Data Out

Northbound

14×2

Data In

Note: This figure is a conceptual block diagram of the AMB’s data flow and clock domains.

Preliminary Data Sheet E0867E20 (Ver. 2.0)

1 2 345 6 7...22

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