Datasheet > EBE11ED8AJWA

EBE11ED8AJWA

更新时间： 2022-12-21 23:24:24

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
29页	242K
描述
1GB Unbuffered DDR2 SDRAM DIMM

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EBE11ED8AJWA 数据手册

EBE11ED8AJWA

Byte No. Function described

Maximum data access time (tAC) from

clock at CL = X − 2

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

60H

0.6ns*¹

-8E, -6E (CL = 3)

-8G (CL = 4)

50H

32H

3CH

1EH

0.5ns*¹

12.5ns

15ns

Minimum row precharge time (tRP)

-8E

-8G, -6E

Minimum row active to row active delay

(tRRD)

7.5ns

Minimum /RAS to /CAS delay (tRCD)

-8E

32H

3CH

2DH

80H

12.5ns

15ns

-8G, -6E

Minimum active to precharge time

(tRAS)

45ns

Module rank density

512M bytes

Address and command setup time

before clock (tIS)

-8E, -8G

17H

20H

25H

27H

05H

0.17ns*¹

0.20ns*¹

0.25ns*¹

0.27ns*¹

0.05ns*¹

-6E

Address and command hold time after

clock (tIH)

-8E, -8G

-6E

Data input setup time before clock

(tDS)

-8E, -8G

-6E

10H

12H

0.10ns*¹

0.12ns*¹

Data input hold time after clock (tDH)

-8E, -8G

-6E

17H

3CH

0.17ns*¹

15ns*¹

Write recovery time (tWR)

Internal write to read command delay

(tWTR)

1EH

7.5ns*¹

Internal read to precharge command

delay (tRTP)

1EH

00H

30H

00H

39H

3CH

69H

80H

14H

18H

1EH

7.5ns*¹

TBD

Memory analysis probe characteristics

Extension of Byte 41 and 42

-8E

-8G, -6E

Undefined

57.5ns*¹

60ns*¹

Active command period (tRC)

-8E

-8G, -6E

Auto refresh to active/

Auto refresh command cycle (tRFC)

105ns*¹

8ns*¹

SDRAM tCK cycle max. (tCK max.)

Dout to DQS skew

-8E, -8G

0.20ns*¹

0.24ns*¹

0.30ns*¹

-6E

Data hold skew (tQHS)

-8E, -8G

-6E

22H

00H

0.34ns*¹

PLL relock time

Undefined

47 to 61

Data Sheet E1054E30 (Ver. 3.0)

1...3 4 567 8 9...29

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