Datasheet > EBE11ED8AJWA

EBE11ED8AJWA

更新时间： 2022-12-21 23:24:24

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
29页	242K
描述
1GB Unbuffered DDR2 SDRAM DIMM

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EBE11ED8AJWA 数据手册

EBE11ED8AJWA

Serial PD Matrix

Byte No. Function described

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

Number of bytes utilized by module

manufacturer

80H

08H

128 bytes

256 bytes

Total number of bytes in serial PD

device

Memory type

08H

0EH

0AH

61H

48H

00H

05H

DDR2 SDRAM

Number of row address

Number of column address

Number of DIMM ranks

Module data width

Module data width continuation

Voltage interface level of this assembly 0

SSTL 1.8V

DDR SDRAM cycle time, CL = X

-8E (CL = 5)

25H

2.5ns*¹

-8G (CL = 6)

-6E (CL = 5)

25H

30H

2.5ns*¹

3.0ns*¹

SDRAM access from clock (tAC)

-8E, -8G

40H

0.4ns*¹

-6E

45H

02H

82H

08H

00H

0.45ns*¹

ECC

7.8µs

× 8

DIMM configuration type

Refresh rate/type

Primary SDRAM width

Error checking SDRAM width

Reserved

× 8

SDRAM device attributes:

Burst length supported

0CH

04H

4,8

SDRAM device attributes: Number of

banks on SDRAM device

SDRAM device attributes:

/CAS latency

38H

3, 4, 5

-8E, -6E

-8G

70H

01H

02H

00H

4, 5, 6

DIMM Mechanical Characteristics

DIMM type information

SDRAM module attributes

4.00mm max.

Unbuffered

Normal

Weak Driver 50Ω

ODT Support

SDRAM device attributes: General

03H

Minimum clock cycle time at CL = X − 1

-8E, -6E (CL = 4)

3DH

30H

3.75ns*¹

3.0ns*¹

-8G (CL = 5)

Maximum data access time (tAC) from

clock at CL = X − 1

-8E, -6E (CL = 4)

50H

0.5ns*¹

-8G (CL = 5)

45H

50H

3DH

0.45ns*¹

5.0ns*¹

Minimum clock cycle time at CL = X − 2

-8E, -6E (CL = 3)

-8G (CL = 4)

3.75ns*¹

Data Sheet E1054E30 (Ver. 3.0)

1 2 3 456 7 8...29

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