Datasheet > EBD11UD8ADDA-E

EBD11UD8ADDA-E

更新时间： 2022-11-25 15:23:22

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
19页	213K
描述
1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)

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EBD11UD8ADDA-E 数据手册

DATA SHEET

1GB DDR SDRAM SO-DIMM

EBD11UD8ADDA-E (128M words × 64 bits, 2 Ranks)

Description

Features

The EBD11UD8ADDA is 128M words × 64 bits, 2

ranks Double Data Rate (DDR) SDRAM Small Outline

Dual In-line Memory Module, mounting 16 pieces of

512M bits DDR SDRAM sealed in TCP package. Read

and write operations are performed at the cross points

of the CK and the /CK. This high-speed data transfer

is realized by the 2 bits prefetch-pipelined architecture.

Data strobe (DQS) both for read and write are available

for high speed and reliable data bus design. By setting

extended mode register, the on-chip Delay Locked

Loop (DLL) can be set enable or disable. This module

provides high density mounting without utilizing surface

mount technology. Decoupling capacitors are mounted

beside each TCP on the module board.

• 200-pin socket type small outline dual in line memory

module (SO-DIMM)

PCB height: 31.75mm

Lead pitch: 0.6mm

Lead-free

• 2.5V power supply

• Data rate: 333Mbps/266Mbps (max.)

• 2.5 V (SSTL_2 compatible) I/O

• Double Data Rate architecture; two data transfers per

clock cycle

• Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

• Data inputs, outputs and DM are synchronized with

DQS

Note: Do not push the cover or drop the modules in

order to avoid mechanical defects, which may

result in electrical defects.

• 4 internal banks for concurrent operation

(Components)

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Data mask (DM) for write data

• Auto precharge option for each burst access

• Programmable burst length: 2, 4, 8

• Programmable /CAS latency (CL): 2, 2.5

• Refresh cycles: (8192 refresh cycles /64ms)

7.8µs maximum average periodic refresh interval

• 2 variations of refresh

Auto refresh

Self refresh

Document No. E0603E10 (Ver. 1.0)

Date Published October 2004 (K) Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2004

12 3 4 5 6 7...19

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