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DS4424

更新时间： 2024-02-26 16:17:26
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
10页 223K
描述
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC

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DS4424 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：DFN
包装说明：HVSON, SOLCC14,.12,16针数：14
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.41最大模拟输出电压：4.75 V
最小模拟输出电压：转换器类型：D/A CONVERTER
输入位码：BINARY输入格式：SERIAL
JESD-30 代码：S-XDSO-N14JESD-609代码：e3
长度：3 mm最大线性误差 (EL)：0.7812%
湿度敏感等级：1位数：7
功能数量：1端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVSON
封装等效代码：SOLCC14,.12,16封装形状：SQUARE
封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
座面最大高度：0.8 mm子类别：Other Converters
最大压摆率：0.25 mA标称供电电压：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.4 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3 mm
Base Number Matches：1

DS4424 数据手册

 浏览型号DS4424的Datasheet PDF文件第1页浏览型号DS4424的Datasheet PDF文件第2页浏览型号DS4424的Datasheet PDF文件第4页浏览型号DS4424的Datasheet PDF文件第5页浏览型号DS4424的Datasheet PDF文件第6页浏览型号DS4424的Datasheet PDF文件第7页 
2
Two-/Four-Channel, I C, 7-Bit Sink/Source  
Current DAC  
/DS24  
OUTPUT CURRENT SOURCE CHARACTERISTICS (continued)  
(V  
CC  
= +2.7V to +5.5V, T = -40°C to +85°C.)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
0.32  
0.42  
0.16  
0.16  
MAX  
UNITS  
DC source  
DC sink  
Output Current Variation Due to  
Power-Supply Change  
%/V  
DC source, V  
measure at 1.2V  
OUT  
Output Current Variation Due to  
Output-Voltage Change  
%/V  
μA  
DC sink, V  
measure at 1.2V  
OUT  
Output Leakage Current at Zero  
Current Setting  
I
-1  
+1  
ZERO  
Output Current Differential  
Linearity  
DNL  
INL  
(Notes 6, 7)  
-0.5  
-1  
+0.5  
+1  
LSB  
LSB  
Output Current Integral Linearity  
(Notes 7, 8)  
AC ELECTRICAL CHARACTERISTICS  
(V  
CC  
= +2.7V to +5.5V, T = -40°C to +85°C.)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
SCL Clock Frequency  
f
(Note 9)  
0
400  
kHz  
SCL  
Bus Free Time Between STOP  
and START Conditions  
t
1.3  
0.6  
μs  
μs  
BUF  
Hold Time (Repeated) START  
Condition  
t
HD:STA  
Low Period of SCL  
High Period of SCL  
Data Hold Time  
t
1.3  
0.6  
μs  
μs  
μs  
ns  
μs  
ns  
ns  
μs  
LOW  
t
HIGH  
t
t
t
0
0.9  
DH:DAT  
SU:DAT  
SU:STA  
Data Setup Time  
100  
START Setup Time  
SDA and SCL Rise Time  
SDA and SCL Fall Time  
STOP Setup Time  
0.6  
t
(Note 10)  
(Note 10)  
20 + 0.1C  
20 + 0.1C  
0.6  
300  
300  
R
B
t
F
B
t
SU:STO  
SDA and SCL Capacitive  
Loading  
C
(Note 10)  
400  
pF  
B
Note 1: All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.  
Note 2: Input resistors (R ) must be between the speciifed values to ensure the device meets its accuracy and linearity specifications.  
FS  
Note 3: Supply current specified with all outputs set to zero current setting. A0 and A1 are connected to GND. SDA and SCL are con-  
nected to V . Excludes current through R resistors (I  
). Total current including I  
is I + (2 x I  
).  
RFS  
CC  
FS  
RFS  
RFS  
CC  
Note 4: The output-voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications.  
Note 5: Temperature drift excludes drift caused by external resistor.  
Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position  
and the actual increase. The expected incremental increase is the full-scale range divided by 127.  
Note 7: Guaranteed by design.  
Note 8: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.  
The expected value is a straight line between the zero and the full-scale values proportional to the setting.  
2
Note 9: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I C standard-mode timing.  
Note 10: C —total capacitance of one bus line in pF.  
B
_______________________________________________________________________________________  
3
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