DS4424

更新时间： 2024-01-03 15:14:15

品牌	Logo	应用领域
美信 - MAXIM		/
页数	文件大小	规格书
10页	223K
描述
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC

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技术参数
数据手册

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DS4424 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	DFN
包装说明：	HVSON, SOLCC14,.12,16	针数：	14
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	6 weeks
风险等级：	5.41	最大模拟输出电压：	4.75 V
最小模拟输出电压：		转换器类型：	D/A CONVERTER
输入位码：	BINARY	输入格式：	SERIAL
JESD-30 代码：	S-XDSO-N14	JESD-609代码：	e3
长度：	3 mm	最大线性误差 (EL)：	0.7812%
湿度敏感等级：	1	位数：	7
功能数量：	1	端子数量：	14
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVSON
封装等效代码：	SOLCC14,.12,16	封装形状：	SQUARE
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	3/5 V	认证状态：	Not Qualified
座面最大高度：	0.8 mm	子类别：	Other Converters
最大压摆率：	0.25 mA	标称供电电压：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.4 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3 mm
Base Number Matches：	1

DS4424 数据手册

Two-/Four-Channel, I C, 7-Bit Sink/Source

Current DAC

/DS24

Example: R

= 80kΩ and register 0xF8h is written to

STOP Condition: A STOP condition is generated by the

master to end a data transfer with a slave. Transitioning

SDA from low to high while SCL remains high generates

a STOP condition. See Figure 1 for applicable timing.

FS0

a value of 0xAAh. Calculate the output current.

= (0.976V/80kΩ) x (127/16) = 96.838µA

The MSB of the output register is 1, so the output is

sourcing the value corresponding to position 2Ah (42

decimal). The magnitude of the output current is equal to:

Repeated START Condition: The master can use a

repeated START condition at the end of one data trans-

fer to indicate that it will immediately initiate a new data

transfer following the current one. Repeated STARTs are

commonly used during read operations to identify a spe-

cific memory address to begin a data transfer. A repeat-

ed START condition is issued identically to a normal

START condition. See Figure 1 for applicable timing.

96.838µA x (42/127) = 32.025µA

I C Serial Interface Description

I C Definitions

The following terminology is commonly used to describe

I C data transfers:

Bit Write: Transitions of SDA must occur during the low

state of SCL. The data on SDA must remain valid and

unchanged during the entire high pulse of SCL, plus the

setup and hold time requirements (Figure 1). Data is

shifted into the device during the rising edge of the SCL.

I C Slave Address: The slave address of the

DS4422/DS4424 is determined by the state of the A0

and A1 pins (see Table 1).

Master Device: The master device controls the slave

devices on the bus. The master device generates SCL

clock pulses and START and STOP conditions.

Bit Read: At the end of a write operation, the master must

release the SDA bus line for the proper amount of setup

time (Figure 1) before the next rising edge of SCL during a

bit read. The device shifts out each bit of data on SDA at

the falling edge of the previous SCL pulse and the data bit

is valid at the rising edge of the current SCL pulse.

Remember that the master generates all SCL clock puls-

es, including when it is reading bits from the slave.

Slave Devices: Slave devices send and receive data

at the master’s request.

Bus Idle or Not Busy: Time between STOP and START

conditions when both SDA and SCL are inactive and in

their logic-high states. When the bus is idle it often initi-

ates a low-power mode for slave devices.

Acknowledgement (ACK and NACK): An Acknowledge-

ment (ACK) or Not Acknowledge (NACK) is always the

ninth bit transmitted during a byte transfer. The device

receiving data (the master during a read or the slave

during a write operation) performs an ACK by transmit-

ting a zero during the ninth bit. A device performs a

START Condition: A START condition is generated by

the master to initiate a new data transfer with a slave.

Transitioning SDA from high to low while SCL remains

high generates a START condition. See Figure 1 for

applicable timing.

SDA

BUF

HD:STA

LOW

SCL

SU:STA

HD:STA

HIGH

REPEATED

START

SU:STO

SU:DAT

STOP

START

HD:DAT

NOTE: TIMING IS REFERENCED TO V

AND V

IL(MAX)

IH(MIN)

Figure 1. I C Timing Diagram

_______________________________________________________________________________________

1...4 5 678 9 10

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