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DS4000A0/WBGA PDF预览

DS4000A0/WBGA

更新时间: 2024-01-08 23:46:15
品牌 Logo 应用领域
达拉斯 - DALLAS /
页数 文件大小 规格书
15页 171K
描述
Oscillator,

DS4000A0/WBGA 技术参数

生命周期:TransferredReach Compliance Code:unknown
风险等级:5.54Base Number Matches:1

DS4000A0/WBGA 数据手册

 浏览型号DS4000A0/WBGA的Datasheet PDF文件第1页浏览型号DS4000A0/WBGA的Datasheet PDF文件第2页浏览型号DS4000A0/WBGA的Datasheet PDF文件第3页浏览型号DS4000A0/WBGA的Datasheet PDF文件第5页浏览型号DS4000A0/WBGA的Datasheet PDF文件第6页浏览型号DS4000A0/WBGA的Datasheet PDF文件第7页 
DS4000  
AC ELECTRICAL CHARACTERISTICS: 2-WIRE SERIAL INTERFACE  
(VCC = 4.75 to 5.25V, TA = -40°C to +85°C)  
PARAMETER  
SYMBOL  
CONDITION  
Fast mode  
MIN  
TYP MAX  
UNITS  
0
0
400  
100  
SCL Clock Frequency  
fSCL  
kHz  
Standard mode  
Fast mode  
1.3  
4.7  
0.6  
Bus Free Time Between  
a STOP and START  
Condition  
tBUF  
µs  
Standard mode  
Fast mode (Note 7)  
Hold Time (Repeated)  
START Condition  
tHD:STA  
µs  
µs  
µs  
Standard mode (Note 7)  
Fast mode  
4.0  
1.3  
Low Period of SCL  
Clock  
tLOW  
Standard mode  
4.7  
Fast mode  
0.6  
4.0  
0.6  
High Period of SCL  
Clock  
tHIGH  
Standard mode  
Fast mode  
Setup Time for a  
Repeated START  
Condition  
tSU:STA  
tHD:DAT  
tSU:DAT  
µs  
µs  
ns  
Standard mode  
4.7  
Fast mode (Note 8)  
Standard mode (Note 8)  
0
0
0.9  
0.9  
Data Hold Time  
Data Setup Time  
Fast mode (Note 9)  
100  
250  
Standard mode (Note 9)  
Fast mode (Note 9)  
Standard mode (Note 9)  
Fast mode (Note 10)  
Standard mode (Note 10)  
Fast mode  
20 + 0.1CB  
20 + 0.1CB  
20 + 0.1CB  
20 + 0.1CB  
0.6  
300  
1000  
300  
Rise Time of Both SDA  
and SCL  
tR  
tF  
ns  
ns  
µs  
Fall Time of Both SDA  
and SCL  
1000  
Setup Time for STOP  
Condition  
tSU:STO  
Standard mode  
4.0  
Capacitive Load for  
Each Bus Line  
CB  
CI  
Note 10  
400  
pF  
pF  
Input Capacitance  
5
Note 7: After this period, the first clock pulse is generated.  
Note 8: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.  
Note 9: A fast-mode device can be used in a standard mode system, but the requirement tSU:DAT >250ns must then be met. This is automatically  
the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL  
signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT (1000 + 250 = 1250ns) before the SCL line is released.  
Note 10: CB: Total capacitance of one bus line in pF.  
4 of 15  

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