ABRIDGED DATA SHEET
DS2465
SHA-256 Coprocessor with 1-Wire Master Function
ELECTRICAL CHARACTERISTICS (continued)
(T = -40NC to +85NC, unless otherwise noted.) (Note 1)
A
PARAMETER
Input Capacitance
SYMBOL
CONDITIONS
MIN
TYP
MAX
10
UNITS
pF
C
(Note 3)
(Note 3)
I
SCL Clock Frequency
f
0
400
kHz
SCL
Hold Time (Repeated) START
Condition; After this Period, the
First Clock Pulse is Generated
t
0.6
Fs
HD:STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
(Note 3)
(Note 3)
1.3
0.6
Fs
Fs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
t
(Note 3)
0.6
Fs
SU:STA
HD:DAT
Data Hold Time
t
(Notes 3, 15, 16)
(Notes 3, 17)
(Note 3)
0.9
Fs
ns
Fs
Data Setup Time
t
250
0.6
SU:DAT
SU:STO
Setup Time for STOP Condition
t
Bus Free Time Between a STOP
and START Condition
t
(Note 3)
1.3
Fs
BUF
Capacitive Load for Each Bus Line
Oscillator Warmup Time
C
(Notes 3, 18)
(Note 12)
400
200
pF
B
t
Fs
OSCWUP
Note 1: Limits are 100% production tested at T = +25°C and/or T = +85°C. Limits over the operating temperature range and
A
A
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: Operating current with 1-Wire write byte sequence followed by continuous read of 1-Wire Master Status register at 400kHz
in overdrive.
Note 3: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note ꢁ: Active pullup or resistive pullup and range are configurable.
Note 5: The active pullup does not apply to the rising edge of a presence pulse outside of a 1-Wire Reset Pulse command or
during the recovery after a short on the 1-Wire line.
Note 6: All 1-Wire timing specifications are derived from the same timing circuit.
Note 7: Current drawn from V
Note ±: Write-cycle endurance is tested in compliance with JESD47G.
during the EEPROM programming interval or SHA-256 computation.
CC
Note 9: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 1ꢀ: Data retention is tested in compliance with JESD47G.
Note 11: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
2
Note 12: I C communication should not take place for the max t
or t
time following a power-on reset or a wake-up
OSCWUP
SWUP
from sleep mode.
Note 13: All I C timing values are referred to V
Note 1ꢁ: I/O pins of the DS2465 do not obstruct the SDA and SCL lines if V
Note 15: The DS2465 provides a hold time of at least 300ns for the SDA signal (referenced to the V
2
and V
levels.
IH(MIN)
IL(MAX)
is switched off.
CC
of the SCL signal) to
IH(MIN)
bridge the undefined region of the falling edge of SCL.
Note 16: The maximum t
has only to be met if the device does not stretch the low period (t
) of the SCL signal. If the
2
HD:DAT
LOW
clock stretches the SCL, the data must be valid by the setup time before it releases the clock (I C bus specification
Rev. 03, 19 June 2007).
2
2
Note 17: A fast-mode I C bus device can be used in a standard-mode I C-bus system, but the requirement t
R 250ns must
SU:DAT
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
+ t
= 1000 +
R(MAX)
SU:DAT
2
250 = 1250ns (according to the standard-mode I C bus specification) before the SCL line is released. Also the acknowl-
2
edge timing must meet this setup time (I C bus specification Rev. 03, 19 June 2007).
Note 1±: C = Total capacitance of one bus line in pF. The maximum bus capacitance allowable may vary from this value depend-
B
2
ing on the actual operating voltage and frequency of the application (I C bus specification Rev. 03, 19 June 2007).
����������������������������������������������������������������� Maxim Integrated Products
ꢁ