Datasheet > DS2465

DS2465

更新时间： 2023-12-20 18:46:09

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
30页	1892K
描述
DeepCover安全认证器具有SHA-256协处理器和1-Wire主机功能

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中文翻译

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数据手册

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DS2465 数据手册

ABRIDGED DATA SHEET

DS2465

DeepCover Secure Authenticator with

SHA-256 Coprocessor and 1-Wire Master Function

slave may refuse to accept data, possibly because of

an invalid command code or unexpected data. In this

case, the slave device does not acknowledge any of

the bytes that it refuses and leaves SDA high. In either

case, after a slave has failed to acknowledge, the mas-

ter first should generate a repeated START condition

or a STOP condition followed by a START condition to

begin a new data transfer.

be sent with the direction bit set to 1. The read address

is determined either from a preceding write access or

implied from a function command.

The DS2465 has different types of memory. Some areas

allow unrestricted read/write access [R/W], others are

write-only [W], read-only [R] or have user-programmable

access restrictions [(R)/(W)].

As a

consequence, the read and write behavior is address

dependent. Figure 11 shows details.

Not Acknowledged by Master: At some time when

receiving data, the master must signal an end of data

to the slave. To achieve this, the master does not

acknowledge the last byte that it has received from the

slave. In response, the slave releases SDA, allowing

the master to generate the STOP condition.

Type 1 Behavior

The common I C random access read/write protocol with

data acknowledge and address auto-increment applies.

Read and Write

To write to the DS2465, the master must access the

device in write access mode, i.e., the slave address must

be sent with the direction bit set to 0. The next byte to be

sent in write access mode is an address byte to select

the register or memory address to be written to or to

set the address for a subsequent read access (dummy

write).

Type 2 Behavior

This behavior applies to the command register, the

address to which commands and parameter bytes are

written, e.g., to activate the SHA engine or to start any

activity on the 1-Wire port. When accessed in write mode,

the address does not increment. The subsequent read

position is implied by the command code that the mas-

ter writes. When accessed in read mode coming from a

lower address, the data read is indeterminate, but the

address increments.

To read from the DS2465, the master must access the

device in read access mode, i.e., the slave address must

ADDRESS

RANGE

READ/WRITE

BEHAVIOR

ACCESS

NOTES

00h to 4Bh

4Ch to 5Fh

60h

R/W

—

Type 1

Type 2

Type 3

Type 4

Scratchpad.

Reserved. Data written is not stored. Data read is indeterminate.

Command register.

61h

1-Wire Master Status.

62h

1-Wire Read Data.

Refer to the full data sheet.

66h

—

R/W

—

Type 1

Type 4

Reserved

67h to 6Dh

6Eh to 6Fh

70h to 73h

74h to 7Fh

80h to BFh

C0h to FFh

1-Wire Configuration.

Reserved. Data written is not stored. Data read is indeterminate.

Factory-programmed data.

—

Reserved. Data read is indeterminate.

User memory.

(R)/(W)

—

Reserved. Data written is not stored. Data read is indeterminate.

Figure 11. Address-Specific Read and Write Behavior

Maxim Integrated

1...21 22 232425 26 27...30

中文翻译

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与DS2465相关器件

型号	品牌	获取价格	描述	数据表
DS2465_13	MAXIM	获取价格	DeepCover Secure Authenticator with SHA-256 Coprocessor and 1-Wire Master Function
DS2465P	MAXIM	获取价格	SHA-256 Coprocessor with 1-Wire Master Function
DS2465P T	MAXIM	获取价格	SHA-256 Coprocessor with 1-Wire Master Function
DS2465P+	MAXIM	获取价格	SHA-256 Coprocessor with 1-Wire Master Function
DS2465P+T	MAXIM	获取价格	SHA-256 Coprocessor with 1-Wire Master Function
DS2475	ADI	获取价格	DeepCover ECDSA Coprocessor with 1-Wire Master
DS2475RAR	SYSTEMSENSOR	获取价格	SpectrAlert Dual Strobe Notification Appliances
DS2475WAR	SYSTEMSENSOR	获取价格	SpectrAlert Dual Strobe Notification Appliances
DS2476	ADI	获取价格	DeepCover安全协处理器
DS2477	ADI	获取价格	具有ChipDNA PUF保护的DeepCover安全SHA-3协处理器

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