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DS2460ST

更新时间： 2024-01-29 12:25:37
品牌 Logo 应用领域
美信 - MAXIM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
9页 211K
描述
SHA-1 Coprocessor with EEPROMAbridged Data Sheet

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DS2460ST 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.31.00.01Factory Lead Time：6 weeks
风险等级：1.3JESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
湿度敏感等级：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3/5 V认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Other Microprocessor ICs
最大压摆率：0.5 mA最大供电电压：5.5 V
最小供电电压：2.7 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
uPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUITBase Number Matches：1

DS2460ST 数据手册

 浏览型号DS2460ST的Datasheet PDF文件第3页浏览型号DS2460ST的Datasheet PDF文件第4页浏览型号DS2460ST的Datasheet PDF文件第5页浏览型号DS2460ST的Datasheet PDF文件第7页浏览型号DS2460ST的Datasheet PDF文件第8页浏览型号DS2460ST的Datasheet PDF文件第9页 
Abridged Data Sheet  
DS2460  
Repeated START Condition  
Repeated starts are commonly used for read accesses to select a specific data source or address to read from.  
The master can use a repeated START condition at the end of a data transfer to immediately initiate a new data  
transfer following the current one. A repeated START condition is generated the same way as a normal START  
condition, but without leaving the bus idle after a STOP condition.  
Data Valid  
With the exception of the START and STOP condition, transitions of SDA may occur only during the LOW state of  
SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required  
setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL, see Figure 6).  
There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL  
pulse.  
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum  
tSU:DAT + tR in Figure 6) before the next rising edge of SCL to start reading. The slave shifts out each data bit on  
SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL  
pulse. The master generates all SCL clock pulses, including those needed to read from a slave.  
Acknowledge  
Usually, a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte.  
The master must generate a clock pulse that is associated with this acknowledge bit. A device that acknowledges  
must pull SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW during the HIGH  
period of the acknowledge-related clock pulse plus the required setup and hold time (tHD:DAT after the falling edge of  
SCL and tSU:DAT before the rising edge of SCL).  
Not Acknowledged by Slave  
A slave device may be unable to receive or transmit data, e.g., because it is busy performing a real-time function,  
such as MAC computation or EEPROM write cycle. In this case the slave device will not acknowledge its slave  
address and leave the SDA line HIGH.  
A slave device that is ready to communicate will acknowledge at least its slave address. However, some time later  
the slave may refuse to accept data, e.g., because of an invalid command or access mode, or to signal a non-  
matching MAC. In this case the slave device will not acknowledge any of the bytes that it refuses and will leave  
SDA HIGH. In either case, after a slave has failed to acknowledge, the master first needs to generate a repeated  
START condition or a STOP condition followed by a START condition to begin a new data transfer.  
Not Acknowledged by Master  
At some time when receiving data, the master must signal an end of data to the slave device. To achieve this, the  
master does not acknowledge the last byte that it has received from the slave. In response, the slave releases  
SDA, allowing the master to generate the STOP condition.  
Figure 6. I²C Timing Diagram  
SDA  
tBUF  
tHD:STA  
tSP  
tF  
tLOW  
SCL  
tSU:STA  
Spike  
Suppression  
tHD:STA  
tR  
tHIGH  
tSU:STO  
tHD:DAT  
tSU:DAT  
NOTE: Timing is referenced  
to VILMAX and VIHMIN  
Repeated  
START  
STOP START  
.
6 of 9  
1...3456789

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