Datasheet > DS2165Q/T&R

DS2165Q/T&R

更新时间： 2024-02-04 03:55:15

品牌	Logo	应用领域
美信 - MAXIM		PC 电信电信集成电路
页数	文件大小	规格书
17页	342K
描述
ADPCM Codec, A/MU-Law, 1-Func, CMOS, PQCC28, PLASTIC, LCC-28

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

DS2165Q/T&R 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	QCCJ,	针数：	28
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.66	Is Samacsys：	N
压伸定律：	A/MU-LAW	滤波器：	NO
JESD-30 代码：	S-PQCC-J28	JESD-609代码：	e0
长度：	11.505 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	28
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	245
认证状态：	Not Qualified	座面最大高度：	4.57 mm
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	ADPCM CODEC
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	11.505 mm	Base Number Matches：	1

DS2165Q/T&R 数据手册

DS2165Q

OVERVIEW

The DS2165Q contains three major functional blocks: a high performance (10 MIPS) DSP engine, two

independent PCM interfaces (X and Y) that connect directly to serial time-division-multiplexed (TDM)

backplanes, and a serial port that can configure the device on-the-fly by an external controller. A 10MHz

master clock is required by the DSP engine. The DS2165Q can be configured to perform either two

expansions, two compressions, or one expansion and one compression. The PCM/ADPCM data interfaces

support data rates from 256kHz to 4.096MHz. Typically, the PCM data rates are 1.544MHz for ꢀ-law and

2.048MHz for A-law. Each channel on the device samples the serial input PCM or ADPCM bit stream

during a user-programmed input time slot, processes the data and outputs the result during a user-

programmed output time slot.

Each PCM interface has a control register that specifies functional characteristics (compress, expand,

bypass, and idle), data format (ꢀ-law or A-law), and algorithm reset control. With the SPS pin strapped

high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a

novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying

system-level interconnect.

With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control

controller is required and all PCM/ADPCM input and output time slots default to time slot 0.

HARDWARE RESET

RST allows the user to reset both channel algorithms and the contents of the internal registers. This pin

must be held low for at least 1ms on system power-up after the master clock is stable to ensure that the

device has initialized properly. RST should also be asserted when changing to or from the hardware

mode. RST clears all bits of the control register for both channels except the IPD bits; the IPD bits for

both channels are set to 1.

SOFTWARE MODE

Connecting SPS high enables the software mode. In this mode, an external host controller writes

configuration data to the DS2165Q by the serial port through inputs SCLK, SDI, and CS (Figure 2). Each

write to the DS2165Q is either a 2-byte write or a 4-byte write. A 2-byte write consists of the

address/command byte (ACB), followed by a byte to configure the control register (CR) for either the X

or Y channel. The 4-byte write consists of the ACB, followed by a byte to configure the CR, and then 1

byte to set the input time slot and another byte to set the output time slot.

ADDRESS/COMMAND BYTE

In the software mode, the address/command byte is the first byte written to the serial port; it identifies

which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must

match that at inputs A0 to A5. If no match occurs, the device ignores the following configuration data. If

an address match occurs, the next 3 bytes written are accepted as control, input and output time slot data.

Bit ACB.6 determines which side (X or Y) of the device is to be updated. The PCM and ADPCM outputs

are tri-stated during register updates.

2 of 17

123 4 5 6 7...17

下载PDF

与DS2165Q/T&R相关器件

型号	品牌	描述	获取价格	数据表
DS2165Q+	MAXIM	ADPCM Codec, A/MU-Law, 1-Func, CMOS, PQCC28, PLASTIC, LCC-28	获取价格
DS2165QL	ETC	Solid-State Recorder	获取价格
DS2165QL/T&R	MAXIM	ADPCM Codec, A/MU-Law, 1-Func, CMOS, PQCC28, PLASTIC, LCC-28	获取价格
DS2165QL+	MAXIM	ADPCM Codec, A/MU-Law, 1-Func, CMOS, PQCC28, ROHS COMPLIANT, PLASTIC, LCC-28	获取价格
DS2165QN	ETC	Solid-State Recorder	获取价格
DS2165QN/T&R	MAXIM	ADPCM Codec, A/MU-Law, 1-Func, PQCC28, PLASTIC, LCC-28	获取价格

与DS2165Q/T&R相关文章

MAX6675资料手册参数详解、引脚配置说明
2024-05-13

4
LM258引脚图及功能介绍、主要参数分析
2024-05-13

2
CD4052资料手册参数详解、引脚配置说明
2024-05-13

4
一文带你了解TPS5430资料手册分析：参数介绍、引脚配置说明
2024-05-13

4

产品中心

服务支持

精选活动

关于我们

帮助中心

DS2165Q/T&R

DS2165Q/T&R 技术参数

DS2165Q/T&R 数据手册

与DS2165Q/T&R相关器件

与DS2165Q/T&R相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

DS2165Q/T&R

DS2165Q/T&R 技术参数

DS2165Q/T&R 数据手册

与DS2165Q/T&R相关器件

与DS2165Q/T&R相关文章

您还可以找

您在本页遇到什么问题？