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DS15BR400TSQ/NOPB PDF预览

DS15BR400TSQ/NOPB

更新时间: 2024-02-01 07:56:22
品牌 Logo 应用领域
德州仪器 - TI 驱动中继器接口集成电路电视驱动器
页数 文件大小 规格书
23页 624K
描述
具有预加重功能的 4 通道 LVDS 缓冲器/中继器 | RTV | 32 | -40 to 85

DS15BR400TSQ/NOPB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC32,.2SQ,20针数:32
Reach Compliance Code:compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.19差分输出:YES
驱动器位数:4高电平输入电流最大值:0.00001 A
输入特性:DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型:LINE TRANSCEIVER
接口标准:GENERAL PURPOSEJESD-30 代码:S-PQCC-N32
JESD-609代码:e3长度:5 mm
湿度敏感等级:3功能数量:1
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C最小输出摆幅:2 V
输出特性:DIFFERENTIAL输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
最大接收延迟:2 ns接收器位数:4
座面最大高度:0.8 mm子类别:Line Driver or Receivers
最大压摆率:215 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
电源电压1-最大:3.6 V电源电压1-分钟:3 V
电源电压1-Nom:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
最大传输延迟:2 ns宽度:5 mm
Base Number Matches:1

DS15BR400TSQ/NOPB 数据手册

 浏览型号DS15BR400TSQ/NOPB的Datasheet PDF文件第1页浏览型号DS15BR400TSQ/NOPB的Datasheet PDF文件第2页浏览型号DS15BR400TSQ/NOPB的Datasheet PDF文件第4页浏览型号DS15BR400TSQ/NOPB的Datasheet PDF文件第5页浏览型号DS15BR400TSQ/NOPB的Datasheet PDF文件第6页浏览型号DS15BR400TSQ/NOPB的Datasheet PDF文件第7页 
DS15BR400, DS15BR401  
www.ti.com  
SNLS224G AUGUST 2006REVISED APRIL 2013  
PIN DESCRIPTIONS (continued)  
Pin  
Name  
TQFP Pin  
Number  
WQFN Pin  
Number  
I/O, Type  
Description  
DIFFERENTIAL OUTPUTS  
(1)  
OUT0+  
OUT0−  
48  
47  
32  
31  
O, LVDS  
O, LVDS  
O, LVDS  
O, LVDS  
Channel 0 inverting and non-inverting differential outputs.  
Channel 1 inverting and non-inverting differential outputs.  
Channel 2 inverting and non-inverting differential outputs.  
Channel 3 inverting and non-inverting differential outputs.  
(1)  
(1)  
(1)  
OUT1+  
OUT1−  
46  
45  
30  
29  
OUT2+  
OUT2−  
42  
41  
28  
27  
OUT3+  
OUT3-  
40  
39  
26  
25  
DIGITAL CONTROL INTERFACE  
PWDN  
PEM  
12  
2
8
2
I, LVTTL  
I, LVTTL  
A logic low at PWDN activates the hardware power down mode (all channels).  
Pre-emphasis Control Input (affects all Channels)  
POWER  
VDD  
3, 4, 5, 7, 10,  
11, 28, 29, 32,  
33  
3, 4, 6, 7, 20,  
21  
I, Power  
VDD = 3.3V, ±10%  
(2)  
GND  
N/C  
8, 9, 17, 18, 23,  
24, 37, 38, 43,  
44  
5
I, Ground Ground reference for LVDS and CMOS circuitry. For the WQFN package, the  
DAP is used as the primary GND connection to the device in addition to the pin  
numbers listed. The DAP is the exposed metal contact at the bottom of the  
WQFN-32 package. It should be connected to the ground plane with at least 4  
vias for optimal AC and thermal performance.  
1,6, 25, 26, 27,  
1, 17,  
No Connect  
30, 31, 34, 35, 18,19,22, 23,  
36 24  
(1) The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15BR400 and  
DS15BR401 are optimized for point-to-point backplane and cable applications.  
(2) Note that for the WQFN package the GND is connected thru the DAP on the back side of the WQFN package in addition to the actual  
pin numbers listed.  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
Copyright © 2006–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Links: DS15BR400 DS15BR401  

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