DS1312 PDF预览

DS1312

更新时间: 2025-08-10 14:57:55
品牌 Logo 应用领域
亚德诺 - ADI 电池控制器
页数 文件大小 规格书
12页 500K
描述
非易失控制器,带有锂电池监测器

DS1312 数据手册

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19-6306; Rev 6/12  
`
DS1312  
Nonvolatile Controller with Lithium Battery Monitor  
FEATURES  
PIN ASSIGNMENT  
. Converts CMOS SRAM into nonvolatile  
memory  
VCCO  
VBAT  
TOL  
GND  
1
2
3
4
8
7
6
5
VCCI  
BW  
VCCO  
VBAT  
TOL  
GND  
1
2
3
4
8
7
6
5
VCCI  
BW  
. Unconditionally write-protects SRAM when  
VCC is out of tolerance  
CEO  
CEI  
CEO  
CEI  
. Automatically switches to battery backup  
supply when VCC power failure occurs  
. Monitors voltage of a lithium cell and  
provides advanced warning of impending  
battery failure  
DS1312 8-Pin DIP  
(300 mils)  
DS1312S-2 8-Pin SOIC  
(150 mils)  
NC  
VCCO  
NC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
NC  
NC  
VCCO  
NC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
NC  
VCCI  
RST  
NC  
VCCI  
RST  
NC  
. Signals low-battery condition on active low  
Battery Warning output signal  
VBAT  
NC  
VBAT  
NC  
16  
NC  
BW  
CEO  
NC  
. Optional 5% or 10% power-fail detection  
. Space-saving 8-pin DIP and SOIC packages  
. Optional 16-pin SOIC and 20-pin TSSOP  
versions reset processor when power failure  
occurs and hold processor in reset during  
system power-up  
NC  
BW  
NC  
TOL  
NC  
15  
14  
13  
12  
11  
TOL  
NC  
CEO  
NC  
GND  
CEI  
NC  
DS1312S 16-Pin SOIC  
(300 mils)  
GND  
CEI  
DS1312E 20-Pin TSSOP  
. Industrial temperature range of -40°C to  
+85°C  
PIN DESCRIPTION  
VCCI  
VCCO  
VBAT  
- +5V Power Supply Input  
- SRAM Power Supply Output  
- Backup Battery Input  
CEI  
- Chip Enable Input  
CEO  
- Chip Enable Output  
- VCC Tolerance Select  
TOL  
BW  
- Battery Warning Output  
(Open Drain)  
RST  
GND  
NC  
- Reset Output (Open Drain)  
- Ground  
- No Connection  
DESCRIPTION  
The DS1312 Nonvolatile Controller with Battery Monitor is a CMOS circuit which solves the application  
problem of converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-  
of-tolerance condition. When such a condition is detected, chip enable is inhibited to accomplish write  
protection and the battery is switched on to supply the RAM with uninterrupted power. Special circuitry  
uses a low-leakage CMOS process which affords precise voltage detection at extremely low battery  
consumption.  
1 of 12  

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