Datasheet > DS1100LC-301+

DS1100LC-301+

更新时间： 2024-02-19 10:55:31

品牌	Logo	应用领域
美信 - MAXIM		逻辑集成电路
页数	文件大小	规格书
7页	131K
描述
Silicon Delay Line

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技术参数
数据手册

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DS1100LC-301+ 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.59	逻辑集成电路类型：	SILICON DELAY LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

DS1100LC-301+ 数据手册

DS1100L

TERMINOLOGY

Period: The time elapsed between the leading edge of the first pulse and the leading edge of the

following pulse.

t_WI(Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the

1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading

edge.

_RISE(Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the

input pulse.

_FALL(Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the

input pulse.

t_PLH(Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input

pulse and the 1.5V point on the leading edge of any tap output pulse.

t_PHL(Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input

pulse and the 1.5V point on the trailing edge of any tap output pulse.

TEST SETUP DESCRIPTION

Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the

DS1100L. The input waveform is produced by a precision pulse generator under software control. Time

delays are measured by a time interval counter (20ps resolution) connected between the input and each

tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements

are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus.

TEST CONDITIONS INPUT:

Ambient Temperature: 25°C ±3°C

Supply Voltage (V_CC): 3.3V ±0.1V

Input Pulse:

High = 3.0V ±0.1V

Low = 0.0V ±0.1V

50Ω max

3.0ns max (measured between 10% and 90%)

500ns (1μs for -500 version)

1μs (2μs for -500 version)

Source Impedance:

Rise and Fall Time:

Pulse Width:

Period:

OUTPUT:

Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on

the rising and falling edge.

Note: Above conditions are for test only and do not restrict the operation of the device under other

data sheet conditions.

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