Datasheet > DS1100LC-301+

DS1100LC-301+

更新时间： 2024-02-01 18:40:31

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DS1100LC-301+ 技术参数

DS1100L

CAPACITANCE

(T_A= +25°C, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Input Capacitance

C_IN

NOTES:

1) Initial tolerances are ± with respect to the nominal value at +25°C and V_CC= 3.3V for both leading and

trailing edge.

2) Temperature and voltage tolerance is with respect to the nominal delay value over the stated temperature

range, and a supply-voltage range of 3.0V to 3.6V.

3) All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP 1

slows down, all other taps also slow down; TAP 3 can never be faster than TAP 2.

4) Intermediate delay values are available on a custom basis. For further information, contact the factory at

custom.oscillators@maxim-ic.com.

5) All voltages are referenced to ground.

6) Measured with outputs open.

7) See Test Conditions section at the end of this data sheet.

8) Frequencies higher than 1MHz result in higher I_CCvalues.

9) At or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e.,

decoupling, layout).

10) The “-75” version is specified and tested with an additional 2ns of tolerance on the specified minimum

input-to-tap delay tolerance parameter for TAP 1. Delay values for TAP 2 to TAP 5 meet data sheet

specifications.

Figure 1. LOGIC DIAGRAM

Figure 2. TIMING DIAGRAM: SILICON DELAY LINE

3 of 7

1 234 5 6 7

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