Datasheet > DS1087LU-450+T

DS1087LU-450+T

更新时间： 2024-02-04 12:06:21

品牌	Logo	应用领域
美信 - MAXIM		/
页数	文件大小	规格书
12页	150K
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Analog Circuit

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技术参数
数据手册

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DS1087LU-450+T 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	,	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.58
模拟集成电路 - 其他类型：	ANALOG CIRCUIT	峰值回流温度（摄氏度）：	NOT SPECIFIED
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

DS1087LU-450+T 数据手册

3.3V Spread-Spectrum EconOscillator

Note 1:

Note 2:

Note 3:

All voltages are referenced to ground.

This is the absolute accuracy of the master oscillator frequency at the default settings.

This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at

= +25°C.

Note 4:

This is the percentage frequency change from the +25°C frequency due to temperature at V = 3.3V.

Note 5:

Note 6:

The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency.

This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally

introduced to allow the oscillator to stabilize. t

is equivalent to approximately 512 master clock cycles and depends

stab

on the programmed master oscillator frequency.

Output voltage swings may be impaired at high frequencies combined with high output loading.

A fast-mode device can be used in a standard-mode system, but the requirement t > 250ns must then be met. This

Note 7:

Note 8:

SU:DAT

is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch

the LOW period of the SCL signal, it must output the next data bit to the SDA line at least t

+ t

= 1000ns +

R MAX

SU:DAT

250ns = 1250ns before the SCL line is released.

After this period, the first clock pulse is generated.

Note 9:

Note 10: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V

of the SCL sig-

IH MIN

nal) to bridge the undefined region of the falling edge of SCL.

Note 11: The maximum t

need only be met if the device does not stretch the LOW period (t

) of the SCL signal.

HD:DAT

LOW

Note 12: C —total capacitance of one bus line, timing referenced to 0.9 x V and 0.1 x V .

Note 13: Typical frequency shift due to aging is 0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr

+125°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5°C peak) followed by 1000hr

max V

biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, and 168hr 121°C/2 ATM Steam/Unbiased

Autoclave.

Typical Operating Characteristics

(V_CC= 3.3V, T = +25°C, unless otherwise noted.)

ACTIVE SUPPLY CURRENT

vs. TEMPERATURE

ACTIVE SUPPLY CURRENT

vs. VOLTAGE

SUPPLY CURRENT vs. PRESCALER

7.5

7.0

6.5

6.0

5.5

5.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

OUTPUT UNLOADED

= 3.3V

FREQUENCY = 66.6MHz

OUTPUT UNLOADED

OE = PDN = V

FREQUENCY = 66.6MHz

OE = PDN = V

15pF LOAD

3.6V

3.3V

2.7V

8.2pF LOAD

4.7pF LOAD

UNLOADED

100

1000

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90

2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6

VOLTAGE (V)

PRESCALER (DECIMAL)

TEMPERATURE (°C)

_____________________________________________________________________

1 2 3 456 7 8...12

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