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DS1087LU-450+T PDF预览

DS1087LU-450+T

更新时间: 2024-02-12 13:16:04
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美信 - MAXIM /
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12页 150K
描述
Analog Circuit

DS1087LU-450+T 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.58
模拟集成电路 - 其他类型:ANALOG CIRCUIT峰值回流温度(摄氏度):NOT SPECIFIED
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

DS1087LU-450+T 数据手册

 浏览型号DS1087LU-450+T的Datasheet PDF文件第5页浏览型号DS1087LU-450+T的Datasheet PDF文件第6页浏览型号DS1087LU-450+T的Datasheet PDF文件第7页浏览型号DS1087LU-450+T的Datasheet PDF文件第9页浏览型号DS1087LU-450+T的Datasheet PDF文件第10页浏览型号DS1087LU-450+T的Datasheet PDF文件第11页 
3.3V Spread-Spectrum EconOscillator  
Table 1. Register Summary  
REGISTER  
ADDR  
BINARY  
FACTORY DEFAULT  
ACCESS  
LO/  
HIZ  
PRESCALER  
02h  
X
X
X
X
J0  
P3  
P2  
A2  
P1  
A1  
P0  
A0  
110- - - - - b  
R/W  
1
1
1
1
ADDR  
0Dh  
3Fh  
X
X
WC  
11110000b  
R/W  
1
1
WRITE EE  
No Data  
X = Don’t care; read as one.  
1
programmed frequency. Although the output frequency  
changes when the dither is enabled, the duty cycle  
does not change.  
Detailed Description  
A block diagram of the DS1087L is shown in Figure 1.  
Output Frequency  
The internal master oscillator can generate a square  
wave with a frequency range of 33.3MHz to 66.6MHz.  
The master oscillator frequency and output frequency  
are factory programmed, although the user can use the  
programmable divider to divide the master oscillator  
frequency by 2x (where x equals 0 to 8).  
The dither is controlled by the J0 bit in the PRESCALER  
register and enabled with the SPRD pin. The maximum  
spectral attenuation occurs when the prescaler is set to  
1. The spectral attenuation is reduced by 2.7dB for  
every factor of 2 that is used in the prescaler. This hap-  
pens because the prescaler’s divider function tends to  
average the dither in creating the lower frequency.  
However, the most stringent spectral emission limits are  
imposed on the higher frequencies where the prescaler  
is set to a low divider ratio.  
Output Control and Power-Down  
Two user control signals control the output. The output-  
enable pin, OE, gates the clock output buffer and the  
PDN pin disables the master oscillator and turns off the  
output for power-sensitive applications (note: the  
power-down command must persist for at least two out-  
put frequency cycles plus 10µs for deglitching purpos-  
es). On power-up, the output is disabled until power is  
stable and the master oscillator has generated 512  
clock cycles.  
A triangle-wave generator injects an offset element into  
the master oscillator to dither its output. The dither rate  
(see Equation 1) is based on the master oscillator fre-  
quency. Figure 2 shows a plot of the output frequency  
versus dither rate.  
f
(1)  
0
DitherRate =  
Both controls feature a synchronous enable, which  
ensures there are no output glitches when the output is  
enabled. The synchronous enable also ensures a con-  
stant time interval (for a given frequency setting) from  
an enable signal to the first output transition.  
4096  
where f = master oscillator frequency  
0
Register Summary  
The DS1087L registers are used to change the dither  
amount, output frequency, and slave address. A sum-  
mary of the registers is shown in Table 1. Once pro-  
grammed into EEPROM, the settings only need to be  
reprogrammed if it is desired to reconfigure the device.  
Spread Spectrum  
The DS1087L can reduce radiated emission peaks. The  
output frequency can be dithered 2% or 4% below the  
OUTPUT FREQUENCY  
PRESCALER Register  
Bit 5:  
Output Low or High-Z. The LO/HIZ bit  
controls the output. During power-down,  
while the output is deactivated, if the  
LO/HIZ bit is set to 0, the output is high-Z.  
If the LO/HIZ bit is set to 1, the output is  
driven low.  
f /N  
O
(f /N) - 4%  
O
DITHER RATE  
2f /4096  
0
f /4096  
O
O
Bit 4:  
Dither Control. The J0 bit controls the  
dither applied to the output. When J0 is  
high, 2% peak dither is selected. When  
J0 is low, 4% peak dither is selected.  
WHERE N = (2X)  
f
0
= FACTORY PROGRAMMED MASTER OSCILLATOR FREQUENCY  
Figure 2. Output Frequency vs. Dither Rate  
_____________________________________________________________________  
8

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