Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS08MB200

DS08MB200

更新时间： 2024-01-12 18:11:56

品牌	Logo	应用领域
美国国家半导体 - NSC		复用器
页数	文件大小	规格书
10页	280K
描述
Dual 800 Mbps 2:1/1:2 LVDS Mux/Buffer

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技术参数
数据手册

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DS08MB200 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC48,.27SQ,20	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	6 weeks
风险等级：	1.25	差分输出：	YES
驱动器位数：	2	高电平输入电流最大值：	0.00001 A
输入特性：	DIFFERENTIAL SCHMITT TRIGGER	接口集成电路类型：	LINE TRANSCEIVER
接口标准：	GENERAL PURPOSE	JESD-30 代码：	S-XQCC-N48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	3	功能数量：	2
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出极性：	TRUE
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC48,.27SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
最大接收延迟：	2.5 ns	接收器位数：	2
座面最大高度：	0.8 mm	子类别：	Other Interface ICs
最大压摆率：	275 mA	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
电源电压1-最大：	3.6 V	电源电压1-分钟：	3 V
电源电压1-Nom：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	最大传输延迟：	2.5 ns
宽度：	7 mm

DS08MB200 数据手册

Interfacing LVPECL to LVDS

Interfacing LVDS to LVPECL

An LVPECL driver consists of a differential pair with coupled

emitters connected to GND via a current source. This drives

a pair of emitter-followers that require a 50 ohm to V_CC-2.0

load. A modern LVPECL driver will typically include the ter-

mination scheme within the device for the emitter follower. If

the driver does not include the load, then an external scheme

must be used. The 1.3 V supply is usually not readily available

on a PCB, therefore, a load scheme without a unique power

supply requirement may be used.

An LVDS driver consists of a current source (nominal 3.5mA)

which drives a CMOS differential pair. It needs a differential

resistive load in the range of 70 to 130 ohms to generate

LVDS levels. In a system, the load should be selected to

match transmission line characteristic differential impedance

so that the line is properly terminated. The termination resistor

should be placed as close to the receiver inputs as possible.

When interfacing an LVDS driver with a non-LVDS receiver,

one only needs to bias the LVDS signal so that it is within the

common mode range of the receiver. This may be done by

using separate biasing voltage which demands another pow-

er supply. Some receivers have required biasing voltage

available on-chip (V_T, V_TTor V_BB).

20157461

FIGURE 2. DC Coupled LVPECL to LVDS Interface

Figure 2 is a separated π termination scheme for a 3.3 V

LVPECL driver. R1 and R2 provides proper DC load for the

driver emitter followers, and may be included as part of the

driver device (Note 16). The DS08MB200 includes a 100 ohm

input termination for the transmission line. The common mode

voltage will be at the normal LVPECL levels – around 2 V.

This scheme works well with LVDS receivers that have rail-

to-rail common mode voltage, V_CM, range. Most National

Semiconductor LVDS receivers have wide V_CMrange. The

exceptions are noted in devices’ respective datasheets.

Those LVDS devices that do have a wide V_CMrange do not

vary in performance significantly when receiving a signal with

a common mode other than standard LVDS V_CMof 1.2 V.

20157463

FIGURE 4. DC Coupled LVDS to LVPECL Interface

Figure 4 illustrates interface between an LVDS driver and a

LVPECL with a V_Tpin available. R1 and R2, if not present in

the receiver (Note 16), provide proper resistive load for the

driver and termination for the transmission line, and V_Tsets

desired bias for the receiver.

20157464

FIGURE 5. AC Coupled LVDS to LVPECL Interface

20157462

FIGURE 3. AC Coupled LVPECL to LVDS Interface

Figure 5 illustrates AC coupled interface between an LVDS

driver and LVPECL receiver without a V_Tpin available. The

resistors R1, R2, R3, and R4, if not present in the receiver

(Note 16), provide a load for the driver, terminate the trans-

mission line, and bias the signal for the receiver.

Note 16: The bias networks shown above for LVPECL drivers and receivers

may or may not be present within the driver device. The LVPECL driver and

receiver specification must be reviewed closely to ensure compatibility

between the driver and receiver terminations and common mode operating

ranges.

An AC coupled interface is preferred when transmitter and

receiver ground references differ more than 1 V. This is a

likely scenario when transmitter and receiver devices are on

separate PCBs. Figure 3 illustrates an AC coupled interface

between a LVPECL driver and LVDS receiver. R1 and R2, if

not present in the driver device (Note 16), provide DC load for

the emitter followers and may range between 140-220 ohms

for most LVPECL devices for this particular configuration. The

DS08MB200 includes an internal 100 ohm resistor to termi-

nate the transmission line for minimal reflections. The signal

after ac coupling capacitors will swing around a level set by

internal biasing resistors (i.e. fail-safe) which is either V_DD/2

or 0 V depending on the actual failsafe implementation. If in-

ternal biasing is not implemented, the signal common mode

voltage will slowly wander to GND level.

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