July 1993
DP8430V/31V/32V-33 microCMOS Programmable
256k/1M/4M Dynamic RAM Controller/Drivers
General Description
Features
Y
On chip high precision delay line to guarantee critical
DRAM access timing parameters
The DP8430V/31V/32V dynamic RAM controllers provide a
low cost, single chip interface between dynamic RAM and
all 8-, 16- and 32-bit systems. The DP8430V/31V/32V gen-
erate all the required access control signal timing for
DRAMs. An on-chip refresh request clock is used to auto-
matically refresh the DRAM array. Refreshes and accesses
are arbitrated on chip. If necessary, a WAIT or DTACK out-
put inserts wait states into system access cycles, including
burst mode accesses. RAS low time during refreshes and
RAS precharge time after refreshes and back to back ac-
cesses are guaranteed through the insertion of wait states.
Separate on-chip precharge counters for each RAS output
can be used for memory interleaving to avoid delayed back
to back accesses because of precharge. An additional fea-
ture of the DP8432V is two access ports to simplify dual
accessing. Arbitration among these ports and refresh is
done on chip.
Y
Y
microCMOS process for low power
High capacitance drivers for RAS, CAS, WE and DRAM
address on chip
Y
Y
Y
Y
On chip support for nibble, page and static column
DRAMs
Byte enable signals on chip allow byte writing in a word
size up to 32 bits with no external logic
Can use a single clock source. Up to 33 MHz operating
frequency
On board Port A/Port B (DP8432V only)/refresh arbitra-
tion logic
Y
Y
Direct interface to all major microprocessors
4 RAS and 4 CAS drivers (the RAS and CAS configura-
tion is programmable)
Largest
DRAM
Direct Drive
Memory
Access
Ports
Ý
Ý
of Pins
of Address
Outputs
Control
(PLCC)
Possible
Capacity
Available
DP8430V
DP8431V
DP8432V
68
68
84
9
256 kbit
1 Mbit
4 Mbit
4 Mbytes
16 Mbytes
64 Mbytes
Single Access Port
10
11
Single Access Port
Dual Access Ports (A and B)
Block Diagram
DP8430V/31V/32V DRAM Controller
TL/F/11118–1
FIGURE 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
Staggered RefreshTM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/11118
RRD-B30M75/Printed in U. S. A.