September 1991
DP8428/NS32828, DP8429/NS32829
1 Megabit High Speed Dynamic RAM Controller/Drivers
General Description
Features
Y
Makes DRAM interface and refresh tasks appear virtu-
ally transparent to the CPU making DRAMs as easy to
use as static RAMs
The DP8428 and DP8429 1M DRAM Controller/Drivers are
designed to provide ‘‘No-Waitstate’’ CPU interface to Dy-
namic RAM arrays of up to 8 Mbytes and larger. The
DP8428 and DP8429 are tailored for 32-bit and 16-bit sys-
tem requirements, respectively. Both devices are fabricated
using National’s new oxide isolated Advanced Low power
Schottky (ALS) process and use design techniques which
enable them to significantly out-perform all other LSI or dis-
crete alternatives in speed, level of integration, and power
consumption.
Y
Specifically designed to eliminate CPU wait states up to
10 MHz or beyond
Y
Eliminates 20 discrete components for significant board
real estate reduction, system power savings and the
elimination of chip-to-chip AC skewing
Y
On-board ultra precise delay line
Y
On-board high capacitive RAS, CAS, WE and Address
drivers (specified driving 88 DRAMs directly)
Each device integrates the following critical 1M DRAM con-
troller functions on a single monolithic device: ultra precise
delay line; 9 bit refresh counter; fall-through row, column,
and bank select input latches; Row/Column address mux-
ing logic; on-board high capacitive-load RAS, CAS, Write
Enable and Address output drivers; and, precise control sig-
nal timing for all the above.
Y
AC specified for directly addressing up to 8 Mbytes
Y
Low power/high speed bipolar oxide isolated process
Y
Downward pin and function compatible with 256k
DRAM Controller/Drivers DP8409A, DP8417, DP8418,
and DP8419
In order to specify each device for ‘‘true’’ worst case operat-
ing conditions, all timing parameters are guaranteed while
the chip is driving the capacitive load of 88 DRAMs includ-
ing trace capacitance. The chip’s delay timing logic makes
use of a patented new delay line technique which keeps AC
Contents
Y
System and Device Block Diagrams
Y
Recommended Companion Components
Y
Device Connection Diagrams and Pin Definitions
Y
Device DifferencesÐDP8428 vs DP8429
g
skew to 3 ns over the full V
perature range of
g
range of 10% and tem-
125 C. The DP8428 and
CC
a
Y
Mode of Operation
(Descriptions and Timing Diagrams)
b
55 C to
§
§
DP8429 guarantee a maximum RASIN to CASOUT delay of
80 ns or 70 ns even while driving an 8 Mbyte memory array
with error correction check bits included. Two speed select-
ed options of these devices are shown in the switching
Y
Application Description and Diagrams
Y
DC/AC Electrical Specifications, Timing Diagrams and
Test Conditions
characteristics section of this document.
(Continued)
System Diagram
TL/F/8649–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
PALÉ is a registered trademark of and used under license with Monolithic Memories, Inc.
C
1995 National Semiconductor Corporation
TL/F/8649
RRD-B30M105/Printed in U. S. A.