DP8391A

更新时间： 2024-01-26 08:48:37

品牌	Logo	应用领域
美国国家半导体 - NSC		网络接口
页数	文件大小	规格书
12页	193K
描述
SNI Serial Network Interface

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技术参数
数据手册

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DP8391A 技术参数

生命周期：	Obsolete	包装说明：	QCCJ,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.82	Is Samacsys：	N
JESD-30 代码：	S-PQCC-J28	长度：	11.43 mm
功能数量：	1	端子数量：	28
最高工作温度：	55 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	座面最大高度：	4.57 mm
最大压摆率：	270 mA	标称供电电压：	5 V
表面贴装：	YES	电信集成电路类型：	ETHERNET TRANSCEIVER
温度等级：	COMMERCIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.43 mm	Base Number Matches：	1

DP8391A 数据手册

2.0 Block Diagram

TL/F/9357–2

FIGURE 1

3.0 Functional Description

The SNI consists of five main logical blocks:

the transmitted frequency to exceed its 0.01% tolerance.

The frequency marked on the crystal is usually measured

a) the oscillatorÐgenerates the 10 MHz transmit clock sig-

nal for system timing.

with a fixed shunt capacitance (C ) that is specified in the

crystal’s data sheet. This capacitance for 20 MHz crystals is

typically 20 pF. The capacitance between the X1 and X2

pins of the SNI, of the PC board traces and the plated

through holes plus any stray capacitance such as the sock-

et capacitance, if one is used, should be estimated or mea-

sured. Once the total sum of these capacitances is deter-

mined, the value of additional external shunt capacitance

required can be calculated. This capacitor can be a fixed

5% tolerance component. The frequency accuracy should

be measured during the design phase at the transmit clock

pin (TXC) for a given pc layout. Figure 2 shows the crystal

connection.

b) the Manchester encoder and differential output driverÐ

accepts NRZ data from the controller, performs Man-

chester encoding, and transmits it differentially to the

transceiver.

c) the Manchester decoderÐreceives Manchester data

from the transceiver, converts it to NRZ data and clock

pulses, and sends them to the controller.

d) the collision translatorÐindicates to the controller the

presence of a valid 10 MHz signal at its input.

e) the loopback circuitryÐwhen asserted, switches encod-

ed data instead of receive input signals to the digital

phase-locked loop.

3.1 OSCILLATOR

The oscillator is controlled by a 20 MHz parallel resonant

crystal connected between X1 and X2 or by an external

clock on X1. The 20 MHz output of the oscillator is divided

by 2 to generate the 10 MHz transmit clock for the control-

ler. The oscillator also provides internal clock signals to the

encoding and decoding circuits.

TL/F/9357–3

Load capacitance specified by the crystal’s manufacturer

Total parasitic capacitance including:

a) SNI input capacitance between X1 and X2 (typically 5 pF)

b) PC board traces, plated through holes, socket capacitances

Crystal Specification

Note 1: When using a Viking (San Jose) VXB49N5 crystal, the external ca-

pacitor is not required, as the C of the crystal matches the input

capacitance of the DP8391A.

Resonant frequency

Tolerance

Stability

20 MHz

0.001% at 25 C

FIGURE 2. Crystal Connection

0.005% 0–70 C

AT-Cut

3.2 MANCHESTER ENCODER AND DIFFERENTIAL

DRIVER

Type

Circuit

Parallel Resonance

The encoder combines clock and data information for the

transceiver. Data encoding and transmission begins with the

transmit enable input (TXE) going high. As long as TXE re-

The 20 MHz crystal connection to the SNI requires special

care. The IEEE 802.3 standard requires a 0.01% absolute

accuracy on the transmitted signal frequency. Stray capaci-

tance can shift the crystal’s frequency out of range, causing

123 4 5 6 7...12

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DP8391AMWC	NSC	IC DATACOM, ETHERNET TRANSCEIVER, UUC21, WAFER, Network Interface	获取价格
DP8391AN	NSC	SNI Serial Network Interface	获取价格
DP8391AN	TI	DATACOM, ETHERNET TRANSCEIVER, PDIP24, 0.300 INCH, PLASTIC, DIP-24	获取价格
DP8391AV	NSC	SNI Serial Network Interface	获取价格
DP8391AVX	TI	DATACOM, ETHERNET TRANSCEIVER, PQCC28, PLASTIC, CC-28	获取价格
DP8391AV-X	TI	DATACOM, ETHERNET TRANSCEIVER, PQCC28, PLASTIC, LCC-28	获取价格

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