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DP8391A

更新时间： 2024-02-25 13:17:24
品牌 Logo 应用领域
美国国家半导体 - NSC 网络接口
页数 文件大小 规格书
12页 193K
描述
SNI Serial Network Interface

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DP8391A 技术参数

生命周期：Obsolete包装说明：QCCJ,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.82Is Samacsys：N
JESD-30 代码：S-PQCC-J28长度：11.43 mm
功能数量：1端子数量：28
最高工作温度：55 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
认证状态：Not Qualified座面最大高度：4.57 mm
最大压摆率：270 mA标称供电电压：5 V
表面贴装：YES电信集成电路类型：ETHERNET TRANSCEIVER
温度等级：COMMERCIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：11.43 mmBase Number Matches：1

DP8391A 数据手册

 浏览型号DP8391A的Datasheet PDF文件第2页浏览型号DP8391A的Datasheet PDF文件第3页浏览型号DP8391A的Datasheet PDF文件第4页浏览型号DP8391A的Datasheet PDF文件第6页浏览型号DP8391A的Datasheet PDF文件第7页浏览型号DP8391A的Datasheet PDF文件第8页 
5.0 Pin Descriptions  
Pin No.  
Name  
(PCC)  
I/O  
Description  
(DIP)  
1
1
COL  
RXD  
CRS  
RXC  
O
Collision Detect Output. A TTL/MOS level active high output. A 10 MHz  
a
output. When no signal is present at the collision input, COL output will go low.  
(
25%–15%) signal at the collision input will produce a logic high at COL  
2
3
4
2
3
4
O
O
O
Receive Data Output. A TTL/MOS level signal. This is the NRZ data output  
from the digital phase-locked loop. This signal should be sampled by the  
controller at the rising edge of receive clock.  
Carrier Sense. A TTL/MOS level active high signal. It is asserted when valid  
data from the transceiver is present at the receive input. It is de-asserted one  
and a half bit times after the last bit at receive input.  
Receive Clock. A TTL/MOS level recovered clock. When the phase-locked loop  
locks to a valid incoming signal a 10 MHz clock signal is activated on this output.  
This output remains low during idle (5 bit times after activity ceases at receive  
input).  
a b  
Mode Select. A TTL level input. When high, transmit and transmit outputs  
are at the same voltage in idle state providing a ‘‘zero’’ differential. When low,  
5
5
SEL  
I
a
b
is positive with respect to transmit in idle state.  
transmit  
6
7
8
9
6–9  
10  
GND  
LBK  
X1  
Negative Supply Pins.  
I
I
Loopback. A TTL level active high on this input enables the loopback mode.  
Crystal or External Frequency Source Input (TTL).  
11  
12  
X2  
O
Crystal Feedback Output. This output is used in the crystal connection only. It  
must be left open when driving X1 with an external frequency source.  
10  
13  
TXD  
I
Transmit Data. A TTL level input. This signal is sampled by the SNI at the rising  
edge of transmit clock when transmit enable input is high. The SNI combines  
transmit data and transmit clock signals into a Manchester encoded bit stream  
and sends it differentially to the transceiver.  
11  
12  
14  
15  
TXC  
TXE  
O
I
Transmit Clock. A TTL/MOS level 10 MHz clock signal derived from the 20  
MHz oscillator. This clock signal is always active.  
Transmit Enable. A TTL level active high data encoder enable input. This signal  
is also sampled by the SNI at the rising edge of transmit clock.  
b
a
13  
14  
16  
17  
TX  
TX  
O
Transmit Output. Differential line driver which sends the encoded data to the  
transceiver. These outputs are source followers and require 270X pulldown  
resistors to GND.  
15  
16  
18  
19  
NC  
No Connection.  
17  
CAP  
VCC  
NC  
O
Bypass Capacitor. A ceramic capacitor (greater than 0.001 mF) must be  
connected from this pin to GND.  
18  
19  
20–23  
Positive Supply Pins. A 0.1 mF ceramic decoupling capacitor must be  
connected across VCC and GND as close to the device as possible.  
20  
24  
No Connection.  
b
a
21  
22  
25  
26  
RX  
RX  
I
I
Receive Input. Differential receive input pair from the transceiver.  
b
a
23  
24  
27  
28  
CD  
CD  
Collision Input. Differential collision input pair from the transceiver.  
5
12345678...12

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