Datasheet > 微控制器和处理器 > 串行 IO/通信控制器> DP83816AVNG-NOPB

DP83816AVNG-NOPB

更新时间： 2024-01-28 07:12:49

品牌	Logo	应用领域
德州仪器 - TI		控制器 PC 以太网局域网（LAN）标准
页数	文件大小	规格书
109页	854K
描述
10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter-II)

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DP83816AVNG-NOPB 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	144
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.81	地址总线宽度：	32
边界扫描：	NO	总线兼容性：	PCI
最大时钟频率：	25 MHz	数据编码/解码方法：	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
最大数据传输速率：	12.5 MBps	外部数据总线宽度：	32
JESD-30 代码：	S-PQFP-G144	长度：	20 mm
低功率模式：	YES	串行 I/O 数：	4
端子数量：	144	最高工作温度：	85 °C
最低工作温度：	-10 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压：	3.63 V
最小供电电压：	2.97 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	20 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, LAN

DP83816AVNG-NOPB 数据手册

浏览型号DP83816AVNG-NOPB的Datasheet PDF文件第10页

2.0 Pin Description (Continued)

PCI Bus Interface

LQFP Pin

Symbol

SERRN

No(s)

Dir

Description

I/O

System Error: This signal is asserted low by DP83816 during address parity errors

and system errors if enabled.

STOPN

TRDYN

I/O

Stop: This signal is asserted low by the target device to request the master device

to stop the current transaction.

Target Ready: As a master, this signal indicates that the target is ready for the data

during write operation and with the data during read operation. As a target, this

signal will be asserted low when the (target) device is ready to complete the current

data phase transaction. This signal is used in conjunction with the IRDYN signal.

Data transaction takes place at the rising edge of PCICLK when both IRDYN and

TRDYN are asserted low.

PMEN/

I/O

Power Management Event/Clock Run Function: This pin is a dual function pin.

The function of this pin is determined by the CLKRUN_EN bit 0 of the CLKRUN

Control and Status register (CCSR). Default operation of this pin is PMEN.

CLKRUNN

Power Management Event: This signal is asserted low by the DP83816 to indicate

that a power management event has occurred. For pin connection please refer to

Section 6.7.

Clock Run Function: In this mode, this pin is used to indicate when the PCICLK

will be stopped.

3VAUX

122

123

PCI Auxiliary Voltage Sense: This pin is used to sense the presence of a 3.3V

auxiliary supply in order to define the PME Support available. For pin connection

please refer to Section 6.7.

This pin has an internal weak pull down.

PWRGOOD

PCI bus power good: Connected to PCI bus 3.3V power, this pin is used to sense

the presence of PCI bus power during the D3 power management state.

This pin has an internal weak pull down.

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