DP83620SQ/NOPB

更新时间： 2024-01-22 15:44:57

品牌	Logo	应用领域
德州仪器 - TI		网络接口电信集成电路电信电路以太网局域网（LAN）标准以太网：16GBASE-T
页数	文件大小	规格书
105页	1311K
描述
DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer

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DP83620SQ/NOPB 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	HVQCCN, LCC48,.27SQ,20
Reach Compliance Code：	compliant	ECCN代码：	5A991.B.1
HTS代码：	8542.39.00.01	Factory Lead Time：	8 weeks
风险等级：	1.27	Is Samacsys：	N
数据速率：	100000 Mbps	JESD-30 代码：	S-PQCC-N48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	2	功能数量：	1
端子数量：	48	收发器数量：	1
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	HVQCCN
封装等效代码：	LCC48,.27SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	2.5/3.3,3.3 V	认证状态：	Not Qualified
座面最大高度：	0.8 mm	子类别：	Network Interfaces
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	ETHERNET TRANSCEIVER
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm	Base Number Matches：	1

DP83620SQ/NOPB 数据手册

DP83620

SNLS339C –JANUARY 2011–REVISED APRIL 2013

www.ti.com

3.3 SERIAL MANAGEMENT INTERFACE

Signal Name

Pin Name

Type

Pin #

Description

MDC

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO

management data input/output serial interface which may be asynchronous

to transmit and receive clocks. The maximum clock rate is 25 MHz with no

minimum clock rate.

MDIO

I/O

MANAGEMENT DATA I/O: Bi-directional management instruction/data

signal that may be sourced by the station management entity or the PHY.

This pin requires a 1.5 kΩ pullup resistor. Alternately, an internal pullup may

be enabled by setting bit 3 in the CDCTRL1 register.

3.4 MAC DATA INTERFACE

Signal Name

Pin Name

Type

Pin #

Description

TX_CLK

MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode

or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz reference clock. The

MAC should source TX_EN and TXD[3:0] using this clock.

RMII MODE: Unused in RMII Slave mode. The device uses the X1

reference clock input as the 50 MHz reference for both transmit and

receive. For RMII Master mode, the device outputs the internally generated

50 MHz reference clock on this pin.

This pin provides an integrated 50 ohm signal termination, making external

termination resistors unnecessary.

TX_EN

I, PD

MII TRANSMIT ENABLE: Active high input indicates the presence of valid

data inputs on TXD[3:0].

RMII TRANSMIT ENABLE: Active high input indicates the presence of valid

data on TXD[1:0].

TXD_0

TXD_1

TXD_2

TXD_3

TXD_0

TXD_1

TXD_2

TXD_3

MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept

data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in

100 Mb/s mode).

RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that

accept data synchronous to the 50 MHz reference clock.

I, PD

RX_CLK

MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for

100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.

RMII MODE: Unused in RMII Slave mode. The device uses the X1

reference clock input as the 50 MHz reference for both transmit and

receive. For RMII Master mode, the device outputs the internally generated

50 MHz reference clock on this pin.

This pin provides an integrated 50 ohm signal termination, making external

termination resistors unnecessary.

RX_DV

RX_ER

RX_DV

RX_ER

O, PD

MII RECEIVE DATA VALID: Asserted high to indicate that valid data is

present on the corresponding RXD[3:0].

RMII RECEIVE DATA VALID: This signal provides the RMII Receive Data

Valid indication independent of Carrier Sense.

This pin provides an integrated 50 ohm signal termination, making external

termination resistors unnecessary.

S, O, PU

MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate

that an invalid symbol has been detected within a received packet in 100

Mb/s mode.

RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever a

media error is detected, and RX_DV is asserted in 100 Mb/s mode.

This pin is not required to be used by a MAC in RMII mode, since the PHY

is required to corrupt data on a receive error.

This pin provides an integrated 50 ohm signal termination, making external

termination resistors unnecessary.

RXD_0

RXD_1

RXD_2

RXD_3

RXD_0

RXD_1

RXD_2

RXD_3

S, O, PD

MII RECEIVE DATA: Nibble wide receive data signals driven synchronously

to the RX_CLK (25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode).

RXD[3:0] signals contain valid data when RX_DV is asserted.

RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven

synchronously to the 50 MHz reference clock.

These pins provide integrated 50 ohm signal terminations, making external

termination resistors unnecessary.

Pin Descriptions

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与DP83620SQ/NOPB相关器件

型号	品牌	描述	获取价格	数据表
DP83620SQE	TI	DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer	获取价格
DP83620SQE/NOPB	TI	DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer	获取价格
DP83620SQX	TI	DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer	获取价格
DP83620SQX/NOPB	TI	DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer	获取价格
DP83630	TI	DP83630 Precision PHYTERâ¢ - IEEE 1588 Preci	获取价格
DP83630SQ	TI	DP83630 Precision PHYTERâ¢ - IEEE 1588 Preci	获取价格

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