Datasheet > DP83265

DP83265

更新时间： 2024-02-28 11:15:41

品牌	Logo	应用领域
其他 - ETC		电信集成电路
页数	文件大小	规格书
76页	536K
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DP83265 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QFP,	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.86
JESD-30 代码：	S-PQFP-G160	JESD-609代码：	e0
长度：	28 mm	功能数量：	1
端子数量：	160	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	3.7 mm
标称供电电压：	5 V	表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	28 mm	Base Number Matches：	1

DP83265 数据手册

1.0 FDDI Chip Set Overview

National Semiconductor’s FDDI chip set consists of five

components as shown in Figure 1-1. For more information

about the other devices in the chip set, consult the appropri-

ate data sheets and application notes.

DP83261 BMAC^TMDevice

Media Access Controller

The BMAC device implements the Timed Token Media Ac-

cess Control protocol defined by the ANSI FDDI X3T9.5

MAC Standard.

DP83231 CRD^TMDevice

Clock Recovery Device

The Clock Recovery Device extracts a 125 MHz clock from

Features

All of the standard defined ring service options

the incoming bit stream.

Full duplex operation with through parity

Features

PHY Layer loopback test

Supports all FDDI Ring Scheduling Classes (Synchro-

nous, Asynchronous, etc.)

Supports Individual, Group, Short, Long and External

Addressing

Crystal controlled

Clock locks in less than 85 ms

Generates Beacon, Claim, and Void frames internally

Extensive ring and station statistics gathering

Extensions for MAC level bridging

DP83241 CDD^TMDevice

Clock Distribution Device

From a 12.5 MHz reference, the Clock Distributon Device

synthesizes the 125 MHz, 25 MHz, and 12.5 MHz clock re-

quired by the BSI, BMAC, and PLAYER devices.

Separate management port that is used to configure and

control operation

Multi-frame streaming interface

DP83265 BSI^TMDevice

System Interface

The BSI Device implements an interface between the

DP83251/55 PLAYER^TMDevice

Physical Layer Controller

The PLAYER device implements the Physical Layer (PHY)

protocol as defined by the ANSI FDDI PHY X3T9.5 Stan-

dard.

BMAC device and a host system.

Features

32-bit wide Address/Data path with byte parity

Features

4B/5B encoders and decoders

Programmable transfer burst sizes of 4 or 8 32-bit words

Framing logic

Interfaces to low-cost DRAMs or directly to system bus

Elasticity Buffer, Repeat Filter and Smoother

Provides 2 Output and 3 Input Channels

Line state detector/generator

Supports Header/Info splitting

Link error detector

Efficient data structures

Configuration switch

Programmable Big or Little Endian alignment

Full duplex operation

Full duplex data path allows transmission to self

Separate management port that is used to configure and

control operation

Confirmation status batching services

Receive frame filtering services

In addition, the DP83255 contains an additional

PHY Data.request and PHY Data.indicate port required

for concentrators and dual attach stations.

Operates from 12.5 MHz to 25 MHz synchronously with

host system

1 234 5 6 7...76

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与DP83265相关器件

型号	品牌	描述	获取价格	数据表
DP83265A	ETC		获取价格
DP83265AVF	NSC	IC,COMMUNICATIONS CONTROLLER,BICMOS,QFP,160PIN	获取价格
DP83265BSI	NSC	BSI⑩ Device (FDDI System Interface)	获取价格
DP83265VF	NSC	IC SPECIALTY TELECOM CIRCUIT, PQFP160, PLASTIC, QFP-160, Telecom IC:Other	获取价格
DP83266	NSC	MACSITM Device (FDDI Media Access Controller and System Interface)	获取价格
DP83266VF	NSC	MACSITM Device (FDDI Media Access Controller and System Interface)	获取价格

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